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070608: IITC2007 airgaps & chip-stacks
Ed’s Threads 070608
Musings by Ed Korczynski on June 08, 2007

IITC 2007: Airgaps & chip-stacks
Airgaps and 3D-stacks were the big news from the 10th International Interconnect Technology Conference (IITC) recently held near the San Francisco airport. Two major new materials was presented—IBM showed rhodium (Rh) electro-chemical deposition (ECD) for ≤32nm contact plugs, and Fujitsu showed nano-clustered silicon (NCS) with low k=2.25 for a dielectric—but most new work involves the same materials combined in clever new ways. Airgap technology was covered in four oral presentations, three posters, and countless informal hallway discussions.

Dan Edelstein, IBM Fellow and manager of BEOL technology strategy at Yorktown Heights, NY, gave an invited talk on the many integration challenges for 32nm node interconnects, including resist poisoning from low-k outgassing, low-k damage removal, and the need for improved thin-film interfaces. “We need to keep adding innovation just to stay on the trend-line,” he commented. For example, the industry has historically seen chronically low SiCOH low-k adhesion on SiCHN barrier layers—regardless of equipment, CVD precursor, or plasma preclean—due to a carbon-rich initial deposition. Adding a diverter-valve to the tool allows for stabilized precursor flow before RF power is turned on, which eliminates the carbon-rich deposition and thus solves the adhesion issue. With subtle integration challenges such as these, IBM has chosen to add airgaps as a side-loop with no new materials, tools, or baseline processes. Airgaps drop k by ~35% for any given dielectric material, Edelstein noted, adding that IBM has “shown this on gapped SiOF and low-k SiCOH, and will do it next on ULK porous SiCOH.”

The IBM airgap process both removes and re-deposits some dielectric material, while most airgap approaches for logic chips rely on removal processes alone. The Crolles2Alliance (CEA-Leti, Freescale, NXP, and ST) uses SiO2 at line-levels and a polymer for the via-levels within the dielectric stack, then HF vapor or wet-etch-chemistries to remove the SiO2. NXP and Dow Chemical showed removal of a thermally degradable polymer (TDP) through a CVD SiOC cap layer to make ~30% airgaps at M2 as part of a keff ~2.5 to hit 32nm node specs.

The Crolles2Alliance also showed some of the integration tricks needed to use porous ULK dielectrics at the 32nm node. Different plasmas may seal pore surfaces to provide barrier properties for long-term reliability: CH4 adds C, NH3 substitutes N for C leading toward SiON compositions, and He/H2 plasmas retain near original stoichiometry. Though Cu bulk resistivity is only ~2.2 µOhm-cm, for 60nm line widths it is ~2.9 and increases with reducing widths. CMOS32 uses 50nm Cu line widths for M1, requiring a self-aligned barrier (SAB) <4nm for EM performance, an ALD barrier and thin-Cu seed for filling, and either a CuSiN or CoWP cap layer.

NEC research labs showed that direct ECD of Cu without a Cu-seed layer provides larger grain size and higher Cu(111) orientation. Damascene structures were first sealed with TiN, then either Ta/Cu or Ru layers were deposited. The TiN barrier layer is definitely needed beneath Ru to block Cu diffusion into the dielectric. Ru PVD using DC magnetron sputtering with Ar gas at room temperature produces high orientation of Ru(002). Since Ru(002) is hexagonal-close-packed, it matches well with the preferred Cu(111) face-centered-cubic orientation such that 40%-50% can be grown directly on Ru in dual-damascene structures. Some day, metal line specifications may include not just dimensions and resistivity, but grain orientation and size-distribution too.

Ibaraki U. and Hitachi presented research showing that higher chemical purity leads to lower resistivity in Cu lines. Increasing both the Cu anode purity from 4N to 9N along with the CuSO4·5H2O purity from 3N to 6N reduced line resistance by 21% in 50nm wide lines, with all other process parameters held constant. The high-purity process increased the average grain size from 70 to 74nm, and significantly reduced the oxygen content in the final annealed Cu lines to <1 wt% from the previous 3-4 wt%.

Based on first principles of thermodynamics, an alloy of Cu/Mn can be annealed to result in self-segregation of Mn to the dielectric/Cu barrier. One fundamental advantage of this process is that no barrier is formed at the bottoms of vias, which minimizes resistance. Toshiba’s R&D; group tested self-aligned Mn barriers with 244-via-chain structures and found one-third the resistance compared to Cu vias using the standard Ta barrier.

Georgia Tech and U. of New Mexico researchers showed that a 60% increase in the total number of wire levels is sufficient to account for ~5x increase in the resistivity of wires. Careful routing and a logical hierarchy seem to go a long way, but eventually the industry must get serious about 3D ICs using chip-stacks.

Patrick Leduc of CEA-Leti provided an overview of the main challenges to realizing high density 3D ICs: bonding with ±1µm alignment at T<400°C, Si thinning to <15µm, and through-silicon via (TSV) diameters <3µm. Thermal management issues may not be too difficult—assuming each transistor contributes 0.7W to a 50 W/cm2 average—since bulk silicon acts as an efficient heat spreader and the metal lines conduct well.

Freescale’s Scott Pozder explained that EDA software tools may be the current biggest limitation to 3D integration, since standard tools cannot even account for metal levels on multiple chips. If you explicitly design for 3D, then models show that multiplicative yield-losses can be avoided or eliminated.

There were ~480 conference attendees this year (plus several hundred additional folks running evening supplier-seminars and exhibit booths). Among the attendees with whom I enjoyed discussions were (in alphabetical order) Al Bergendahl, Chris Case, Paul Feeney, Terry Francis, Mike Fury, Xiao Hu Liu, Steven Luce, Satya Nitta, Mike Shapiro, and a special appearance by casually retired Mike Thomas.


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070608: IITC2007 airgaps & chip-stacks

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.