tag:blogger.com,1999:blog-320651062008-06-13T09:23:14.510-07:00SST's Ed's Threads - A Blog on Semiconductor Manufacturing Technology and BusinessSST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comBlogger73125tag:blogger.com,1999:blog-32065106.post-5518398040066576972008-06-13T09:07:00.000-07:002008-06-13T09:20:20.585-07:00080613: Process integration drives the IC industryEd’s Threads 080613
The last musings in this blog on Friday the 13th of June, 2008
Process integration drives the IC industry
The next 10 years will witness more changes in mainstream manufacturing technology for ICs than in the last 40 years combined. An industry based on “what have you done for me lately” can never rest on its laurels, and so innovation must continue, despite limits in 2D SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-63562658767871246882008-06-03T01:52:00.000-07:002008-06-03T02:00:20.785-07:00080602: IITC shows the way to 3DEd’s Threads 080602
Musings by Ed Korczynski on June 2, 2008
IITC shows the way to 3D
The 11th International Interconnect Technology Conference (IITC) started today in Burlingame near the San Francisco airport. Once again, the leading-edge of on-chip interconnect technology developments were presented, with details on new materials, processes, and structures. 3D interconnects and through-siliconSST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-51160630590060321292008-05-19T22:18:00.000-07:002008-05-21T12:34:45.415-07:00080519: Resistive memory resists definitionEd’s Threads 080519
Musings by Ed Korczynski on May 19, 2008 (updated May 21)
Resistive memory resists definition
My recent blog entry about "memristors" and ReRAMs generated a lot of feedback (both on and off the record). The prevailing opinion seems to be that many companies have been working on resistive memory cells for many years, and most of the complex oxide structures at the core of SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-59919223729256128182008-05-14T10:54:00.000-07:002008-05-14T11:02:50.585-07:00080512: SAIL to flyEd’s Threads 080512
Musings by Ed Korczynski on May 12, 2008
SAIL to fly at 5 meters/min
The highlight of the April 16 North California Chapter of the American Vacuum Society’s (NCCAVS) Thin-Film Users Group (TFUG) meeting on printable electronics was the detailed technology presentation on self-aligned imprint lithography (SAIL) as developed by HP and PowerFilm Solar for their roll-to-roll (R2RSST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-24979081788380480622008-05-06T11:03:00.000-07:002008-05-06T11:08:00.870-07:00080505: When is a Memristor a ReRAM?Ed’s Threads 080505
Musings by Ed Korczynski on May 5, 2008
When is a Memristor a ReRAM?
HP published that they are the first to have fabricated a novel circuit element first predicted in 1971 called the “memristor.” The HP authors claim that, “until now no one has presented either a useful physical model or an example of a memristor.” HP is certainly leading the world, but as one of many SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-59750662987000413372008-04-29T11:45:00.000-07:002008-04-29T12:01:24.303-07:00080429: SAFC Hitech opens modular scalable plantEd’s Threads 080429
Musings by Ed Korczynski on April 29, 2008
SAFC Hitech opens modular scalable plant
A trusted supplier of specialty materials for semiconductor manufacturing must have great safety, control, and smarts. These specialty chemicals include precursors for growth and deposition, photoresist and slurry additives, as well as CMP, ECD, encapsulation, packaging and assembly, fuel cellSST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-53700580379018294702008-04-14T23:09:00.000-07:002008-04-14T23:17:00.996-07:00080414: Energy Costs mean externalities matterEd’s Threads 080414
Musings by Ed Korczynski on April 14, 2008
Energy Costs mean externalities matter
What do the words “Energy” and “Costs” have to do with materials considerations in 2008? The most recent issue of the Materials Research Society (MRS) Bulletin has just been released and it’s a special issue devoted to exploring all aspects—including costs—of materials science and engineering SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-79224813794371327332008-04-07T23:17:00.000-07:002008-04-07T23:37:50.229-07:00080407: CNT and graphene dreams may be realEd’s Threads 080407
Musings by Ed Korczynski on April 7, 2008
CNT and graphene dreams may be real
Carbon nano-tubes (CNT) are the only viable (pun-intended) new materials being developed to replace copper as the electrical interconnects for future ICs. There are no known room-temperature superconductors, and optical interconnects require relatively slow and expensive lasers and detectors, and SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-69391224956830494062008-03-31T21:22:00.000-07:002008-03-31T21:25:59.112-07:00080331: MRS meeting covers nanostuff and microthingsEd’s Threads 20080331
Musings by Ed Korczynski on March 31, 2008
MRS meeting covers nanostuff and microthings
Over 4000 researchers were in San Francisco last week for the annual Materials Research Society (MRS) spring meeting, to discuss advances in materials for electronics, energy, health, and transportation. Over 40 technical session run in parallel, with >10 sessions of interest to the SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-42019542631554450232008-03-25T00:55:00.000-07:002008-03-25T00:59:55.207-07:00080324: Etching new IC materials at 32 and 22nmEd’s Threads 080324
Musings by Ed Korczynski on March 24, 2008
Etching new IC materials at 32 and 22nm
Silicon Valley was once the center of the silicon-based IC manufacturing world, and though IC fabs are now located globally the valley maintains momentum as the center of IC R&D. The North-California Chapter of the American Vacuum Society (NCCAVS) still runs regular users groups on important SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-67328241682655065402008-03-17T22:12:00.000-07:002008-03-17T22:17:14.426-07:00080317: There is no more noise...Ed’s Threads 080317
Musings by Ed Korczynski on March 17, 2008
There is no more noise...
There is only signal. In controlling the manufacturing processes used for advanced nano-scale IC, the aspects of metrology which we used to be able to ignore as “just noise” are now essential signal we must control. Where to draw the line, and how close is close are just some of the challenges in ensuring SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-75207290541303207312008-03-04T11:21:00.000-08:002008-03-04T11:28:45.408-08:00080304: DFM matures along with industryEd’s Threads 080304
Musings by Ed Korczynski on March 4, 2008
DFM matures along with industry
Hundreds of technologists over-packed the room in the San Jose Convention Center at 8am on the fourth day of SPIE to hear keynotes from IBM, Intel, and TSMC on the real reality of design for manufacturability (DFM) in the IC fab industry. As the two leading integrated device manufacturers (IDM) in DFM, SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-49454303717370198872008-02-26T00:48:00.001-08:002008-02-26T00:53:24.553-08:00080225: Interconnect technology matureEd’s Threads 080225
Musings by Ed Korczynski on February 25, 2008
Interconnect technology mature
On-chip interconnects made primarily of copper metal insulated with SiOC low-k dielectric material are the current state-of-the-art for the commercial IC manufacturing industry. A report from the TECHCET Group quantifies the materials that are forecasted to be needed to form interconnects for 65nm toSST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-76242975724644988902008-02-19T13:09:00.001-08:002008-02-19T13:17:30.254-08:00080222: TSV forecast for millions of wafersEd’s Threads 080222
Musings by Ed Korczynski on February 22, 2008
TSV forecast for millions of wafers
Through-silicon vias (TSV) can be used to connect 3D multi-chip module stacks with improved performance and reduced timing delays. A new report by analysts at TechSearch International, Through Silicon Via Technology: The Ultimate Market for 3D Interconnect, provides a forecast for millions of SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-10714441867112070392008-02-12T10:23:00.000-08:002008-02-12T10:26:36.316-08:00080211: IITC process units and integrationEd’s Threads 080211
Musings by Ed Korczynski on February 11, 2008
IITC process units and integration
The International Interconnect Technology Conference (IITC) has issued its 11th call for papers, and for a change it will explicitly focus on unit processes (and new materials) while continuing to cover the leading edge of integration. The main deadline for paper submissions has now passed, but aSST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-52047379860657470082008-01-22T02:11:00.000-08:002008-01-22T02:45:35.707-08:00080121: SMC highlights PV, LED, and packaging materialsEd’s Threads
Musings by Ed Korczynski on January 21, 2008
[Happy Birthday, Martin Luther King, Jr.!]
SMC highlights PV, LED, and packaging materials
Last week saw hundreds of microelectronics industry executives gather at ISS and SMC. The conventional forecasts for semiconductor manufacturing equipment and materials have been covered by previous WaferNEWS stories. SMC showed truly amazing SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-41893320277238550052008-01-14T22:04:00.000-08:002008-01-16T07:49:18.924-08:00080111: Flood of used 200mm toolsEd’s Threads 080111
Musings by Ed Korczynski on January 11, 2008
Flood of used 200mm tools
Semico Research, working with affiliated Semiconductor Partners, has released a new study of the near-term forecast for used 200mm wafer processing tools soon to flood the market. In addition to identifying companies that are likely to either purchase or sell a fab and their expansion or divestiture plans,SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-62641381243166533692008-01-03T14:29:00.000-08:002008-01-03T14:48:52.428-08:00080101: 2007 odds and endsEd’s Threads 080101
Musings by Ed Korczynski on January 01, 2008
2007 odds and ends
High-k (HK) and metal-gates (MG) for CMOS transistors are real and here now, with Intel deciding on HK-first but MG-last for process integration. What is the temperature limit for MG processing such that the HK remains amorphous in this flow, and how many other elements are alloyed with hafnium and oxygen in the SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-53582755160301201822007-12-18T11:02:00.000-08:002007-12-18T11:07:35.201-08:00071217: Post-FET future discussed at IEDMEd’s Threads 071217
Musings by Ed Korczynski on December 17, 2007
Post-FET future discussed at IEDM
Silicon-based CMOS FETs will still be used in commercial ICs in twenty years, but it’s likely that completely new devices will also be in production. It seems highly likely that nMOS and pMOS FET “switches” will be used for mainstream logic and memory until 2015-2020, when such things as cross-barSST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-14303842536459932442007-12-11T08:23:00.000-08:002007-12-13T12:45:28.960-08:00071211: HK+MG real details shown at IEDM Ed’s Threads 071211
Musings by Ed Korczynski on December 11, 2007
It’s time for IEDM, and ~1600 leaders of the CMOS fab world have gathered in Washington D.C. to announce the latest, greatest in new devices. The first big news concerns high-k/metal-gate (HK+MG) transistors for 45nm node and beyond processing. With many parallel sessions covering the most important technology trends in IC SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-25418322281786908952007-11-30T07:30:00.000-08:002007-12-13T12:46:41.253-08:00071130: PV perspective: Interview with AMAT's solar technology expert Ed’s Threads 071130
Musings by Ed Korczynski on November 23, 2007
PV perspective: Interview with AMAT's solar technology expert Dr. Charles F. Gay, currently VP and GM of Applied Materials’ solar business group, is a renowned expert in PV technology and business, having been president of Arco Solar, Siemens Solar, and ASE Americas, as well as director of the US Department of SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-33490635136662707752007-11-23T12:04:00.000-08:002007-11-23T12:08:53.878-08:00071123: Printed silicon RF-IDs by KovioEd’s Threads 071123
Musings by Ed Korczynski on November 23, 2007
Printed silicon RF-IDs by Kovio
Humans like to tag and track things. This natural tendency has led from physical tags and labels to bar-codes and today radio-frequency identity (RF-ID) chips. There has been controversy over the possibly use of “active” RF-ID tags being used to secretly track people, but simpler “passive” RF-IDs SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-11998642956053918432007-11-13T12:34:00.000-08:002007-11-13T12:39:38.557-08:00071102: Leti continues to lead researchEd’s Threads 071102
Musings by Ed Korczynski on November 02, 2007
Leti continues to lead research
Leti (Laboratoire d’electronique et de technologie de l’information) is conceptually 1/3 of CEA (Commissariat a l’Energie Atomique), with nuclear energy and nuclear bombs the other major sections. The atomic reactors at the Grenoble site have been shut-down and now the entire sprawling campus is SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-58463813268849660022007-10-30T13:40:00.000-07:002007-10-30T14:49:00.563-07:00071026: Soitec catalyzes SOI consortiumEd’s Threads 071026
Musings by Ed Korczynski on 26 October 2007
Soitec catalyzes SOI consortium
Earlier this month after the SEMICON Europa show, Soitec COO Pascal Mauberger, led me on a tour of the company’s two manufacturing and one R&D lines in Bernin, France across the creek from ST in Crolles. Soitec has taken a bit of a gamble on expanding capacity with a new line in Singapore, just when SST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.comtag:blogger.com,1999:blog-32065106.post-71683131782439988342007-10-15T08:31:00.000-07:002007-10-15T08:35:26.821-07:00071012: Managing mature fabsEd’s Threads 071012
Musings by Ed Korczynski on October 12, 2007
Managing mature fabs
Associated with SEMICON Europe 2007, the Fab Manager’s Forum gathered representatives of Europe’s semiconductor fabs to discuss operations of primarily mature fabs. Michael Lehnert, of Renesas Semiconductor, presented examples of the benefits derived from fault detection besides yield improvement in mature fabsSST's Ed's Threadshttp://www.blogger.com/profile/07666310994401100920noreply@blogger.com