Musings by Ed Korczynski on 12 December 2006
As the semiconductor manufacturing industry has moved to ever smaller device geometries, both new architectures and new materials have been under consideration. The most powerful new transistor architecture for CMOS is the finFET -- also known as multigate FET (MGFET) or trigate FET (triFET) -- which may be thought of as a thin fin of silicon around which wraps the transistor gate material. The IEEE International Electron Devices meeting
(IEDM) 2006 (Dec. 11-13, San Francisco, CA) includes a lot of detailed presentations on finFETs as well as on fin structures for RAM cells.
IEDM 2006 Sessions #27 and #34 include many details of finFET integration. IMEC shows the effects of line-edge-roughness variation on mismatch in 55nm finFET SRAM arrays. SEMATECH and Freescale, IBM, TI, U. of Tokyo, and Oki Electric present work on finFETs. Samsung impressively touts a bulk finFET architecture for 40nm DRAM and beyond. Toshiba shows a high-performance logic finFET using dopant-segregated Schottky source/drain technology to achieve 960uA/µm electron drive current with leakage current in the off state of 100nA/µm for fins with both widths and gate lengths of 15nm.
Reliability tests are critical to ensure that what looks good in a lab will keep looking good out in the real world. Samsung shows a finFET structure for NAND flash memory with gate length of 63nm using TaN gate and fin width of 25nm. After 5K program/erase cycles at 200°C over two hours, the finFET memory cell drive current is 3x greater and the memory window is improved 43% compared to a planar structure using the same materials.
Nanowires can be seen as the ultimate 3D structures for transistors, with the gate all around (GAA) the channel. Two papers from the Institute of Microelectronics and CEA-LETI demonstrate vertically stacked, GAA arrays of “nano-beams” -- LETI’s array shows 6x more current flow compared to a planar transistor using the same contact area.
In an exclusive interview with WaferNEWS, Mike Mayberry, Intel’s director of components research and VP of its Technology and Manufacturing Group, explained that many chips today use a lot of embedded memory and even more will be needed going forward. On-die caching memory needs to be significantly faster than main memory access, and dense enough to hold sufficient code and data. Starting from the manufacturing steps needed to form finFETs, Intel cut off the tops of the fins so that the remaining two sides form double-gates to control charge storage in a floating-body cell. Intel calls this “Independently controlled Double-Gate Floating-Body Cell” (IDG FBC) memory -- but I prefer the far less accurate yet infinitely more memorable term “finRAM.”
Tied to the finFET manufacturing process flow, Intel will use finRAM cache when it uses finFETs for logic, which will not happen before the 32nm node. Regarding extendibility, Mayberry says that “We’ve patterned stuff down to 10nm.” Memory cells built to date have been on SOI wafers, but Intel is still comparing the cost-performance trade off with bulk silicon.
The move from 2D to 3D structures for mainstream CMOS has already occurred with elevated source/drain, and a 3D fin formation process module can be similar in complexity. Fins function for both CMOS logic transistors and floating-body memory cells, but they still aren’t likely to be seen before the 32nm node. -- E.K.
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061212: Fabulous future for finFETs and finRAMs