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080211: IITC process units and integration
Ed’s Threads 080211
Musings by Ed Korczynski on February 11, 2008

IITC process units and integration
The International Interconnect Technology Conference (IITC) has issued its 11th call for papers, and for a change it will explicitly focus on unit processes (and new materials) while continuing to cover the leading edge of integration. The main deadline for paper submissions has now passed, but a limited number of late papers will be accepted until April 11th. The shift in emphasis toward covering unit processes is due to the divergence of integration options moving forward.

Manufacturing ICs on silicon wafers is very complex; hundreds of “unit process” steps (e.g., clean, inspection, etch, deposition, etc) are combined into dozens of “integrated process modules” to form functional structures. One integrated process module may form high-performance transistors, another module forms contacts to transistors, and yet another module forms interconnects between contacts. Many of the unit process steps are copied between modules, and thus has it been since the 1960s.

During the last twenty years, the digital CMOS shrink has been the one process integration direction uniting all the different unit processes under development. The set of requirements for the next node/generation of digital CMOS was always the most challenging for equipment manufacturers working on unit processes. However, starting with the 45nm node, the integration of unit processes has become so complex that there is no one obvious solution for all fabs.

Dr. Thomas Caulfield, EVP of sales, marketing, and customer service for Novellus Systems and former technology executive with IBM, talked with WaferNEWS about the changes in the development of unit-processes in the industry. “As an industry becomes commoditized, how to you differentiate? You either have more efficient design, or more efficient unit processes that allow you to get more productivity or functionality out of the manufacturing. So the last thing you want is the same integrated process,” explained Caulfield. With the leading-edge of IC manufacturing ever increasing in complexity, the productivity of tools used in the fab must increase just to keep costs the same.

Consider the process module to form contacts as an example of integration. Today, the formation of advanced contacts requires something like the following sequence of unit processes:

1) CVD of a blanket dielectric layer,
2) Thermal treatment to stabilize/planarize,
3) Metrology to inspect the layer,
4) Photoresist mask spin-on and bake,
5) Lithography to form initial openings,
6) Treatment to shrink the opening,
7) Metrology to inspect the photoresist,
8) Etch of the dielectric through the mask,
9) Strip/Ash the remaining photoresist,
10) Clean/Treat the dielectric openings,
11) Metrology to inspect openings,
12) Deposit metal barrier layer,
13) Deposit metal for contact,
14) CMP of metal layers, and
15) Metrology to inspect contacts.

Each of these steps has sub-steps too.

In the past, major developments could be described and documented at the integrated process module level, allowing much of the unit process details to be IP secrets. The amazing innovation that enabled digital CMOS shrinks is now pushing against limits of atoms and wavelengths of light, and it now seems clear that further pushes will be ever more expensive. Fabs will also work to integrate analog, RF circuitry, integrated passives, and 3D packages using essentially the same unit processes. “It’s no longer Moore’s Law one-size-fits-all with all the focus on the next generation technology,” explained Caulfield.

Since the integrated process details are now quite sensitive, technologists are relatively more able to talk about developments in unit processes. From an equipment supplier perspective, of course, unit process development does not occur in isolation. “You develop a process capability because you have an application and market in mind,” explains Caulfield. “It’s not that we don’t keep doing that, but today we find customers using the same unit processes in novel ways.”

EDN’s Ron Wilson recently blogged about the IITC call-for-papers and the ramifications of unit process development for IC designers. He considers that porting a physical design from one fab to another may soon require significant inputs from equipment manufacturers, but it is highly unlikely that designers will ever have to talk to OEMs about GDSII files. Using the example of the contact module, the variations in the geometry of the metal contact plug are due to the interdependencies between the different unit processes. Sometimes the source of a structural variation can be easily identified as one unit process, but more often it is impossible to separate out which of the unit processes were to blame. If the diameter of the contact is too large, was the resist overexposed, or was the dielectric overetched?

In addition to the complexity that can be seen in final device structures on the atomic-scale, there are many sacrificial thin-film layers and other “hidden” unit processes within the integrated flow. “It’s funny to watch people debate how something was done based on the data from reverse engineering a final chip,” commented Caulfield. “There’s just no way to conclusively determine the process sequence afterwards with so many sacrificial steps in the integration scheme.”

For example, Novellus sells a pseudo-ALD dielectric tool that forms what they call a pulsed-deposition layer (PDL). Some DRAM fabs use a sacrificial dielectric which they remove with a wet etch, and for this integration scheme the PDL provides no advantage. However, other DRAM fabs use CMP to remove the equivalent sacrificial dielectric, and for them the PDL provides an advantage. The reasons for choosing one integration approach over another are very complex. “People are leveraging unit processes in different ways to try to get the best results while going to higher density,” explained Caulfield. “Productivity or manufacturability differentiation through proprietary integration schemes is the goal—and there are many ways to skin the cat—that provides competitive advantage.”

OEMs have always sold tools that perform basic unit processes, and fabs have always fine-tuned unit processes for integration into modules. The only fundamental change now is that fabs must manage extreme complexity at the same time that most chips have become commodities. “It’s a big problem that the industry is adding manufacturing complexity at the same time that chips are becoming commoditized,” expressed Caulfield. “If you’re not on a curve to take cost out of running a manufacturing tool, then you’ll become the problem that gets worked out of the equation next.”


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080211: IITC process units and integration

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071012: Managing mature fabs
Ed’s Threads 071012
Musings by Ed Korczynski on October 12, 2007

Managing mature fabs
Associated with SEMICON Europe 2007, the Fab Manager’s Forum gathered representatives of Europe’s semiconductor fabs to discuss operations of primarily mature fabs. Michael Lehnert, of Renesas Semiconductor, presented examples of the benefits derived from fault detection besides yield improvement in mature fabs. Renesas Semiconductor Europe Landshut (RSEL) has a 200mm line with 13-15k wspm running 0.5 to 0.15 µm for MCUs (the line was originally a DRAM line).

Fault Detection and Classification (FDC) is a challenge for a fab running several hundred products, with 10 to 100 parameters/tool resulting in up to 5 GB/day of data. With 300,000 SPC charts and 10 entries per chart, and with the data normally distributed and applied 3-sigma limits with a 0.3% false alarm rate, a fab must handle ~1000 false alarms every day. Manufacturing engineers need to change how they work, spending more time with abstract analyses looking at computer screens, and less time crawling through the fab poking at tools. Monitoring facilities parameters such as gas flows and pressures may provide additional relevant data streams.

FDC improvement in wafer-scrap yield was expected, but an additional benefit has been in engineering productivity, with gathering time reduced and more accurate data. Spare-parts and consumables evaluation is now easier, so there is greater confidence in being able to change to less expensive sources when possible. Greater confidence allows for reduction in sampling frequency and reduces the need for dummy wafers. Better preventative maintenance (PM) planning—for example monitoring the filament current in an implanter—results in reduced consumables costs, equipment uptime, and even turn-around time (TAT) due to greater tool availability.

Dr. Detlef Nagel, Sr. Director Product Engineering, Qimonda Dresden discussed how to manage APC in worldwide DRAM fabs. Future business requires an evolution from APC to predictive process control (PPC), which will in turn require a revolution in data-mining, multi-variate control, and yield prediction. Technology complexity can be kept under control by generic run-to-run (R2R) controllers and virtual metrology.

Qimonda uses SMIC and Winbond as foundries to balance production, along with their own fabs in Europe, the US, and Malaysia. Fast distribution of knowledge is a problem due to regional cultural differences, and the inherent difference between development and volume fabs. One innovative solution is the use of a network of senior equipment engineering specialists, with individuals responsible for an assigned toolset within some areas of expertise. This worldwide captive network improves equipment throughput and reliability at Qimonda fabs; there is traditional information exchange with the foundry partners but not the expert knowledge.

Peter Schaffler, global yield enhancement manager for TI, talked about yield enhancement in the Freising fab. It was originally a 3” Bosch fab, and has been continually upgraded to the current level of 0.2µm processing on 200mm wafers; the line runs CMOS/BiCMOS with 20k active reticles used on 400k wafers/year. TI now does tool qualification with product wafers, challenging costs and tool availability. Sampling strategy directly affects your costs: too much wastes expenses, while too little guarantees lost yield. Typical these days is 10-20% of lot starts, but sampling frequency should be determined by the number of lots at risk and the complexity of the mask level, which results in tool-specific dynamic sampling. Or course, an efficient data analysis system is needed to provide macros for data drill-downs using tool, parametric metrology, final electrical test, and other data sets. Proper charting and visualization in an interactive GUI allows new analyses to be done.

Single-wafer tracking allows for the extraction of yield-loss signatures like the wafer number in the lot, first or last wafer effects, and different lots with single wafer excursions. For example, electrical-test data that may originally show no signature can be sorted to obtain a clear clustering of parameters into groups of five wafers, which in turn could point directly at a TEL furnace which was the only toolset running batches of five.

A breakout session on the dynamics of the used equipment market provided a fantastic perspective on the status of the current market. In addition to third-party brokers, OEMs now provide refurbished tools with full one-year warrantees for typically 40-80% of the original selling price. As always, the price is set by markets: the price to acquire the tool, cost to properly refurbish, and the customer demand for the tool. At the high-end of pricing, the used tool is sold with all new tool specs and it may then be considered as almost just another new tool for capacity. If the market forces align in certain ways, even a used 150mm tool may be sold for US$2M.

If you buy through a broker, it is somewhat common to then have to purchase a use license (often for the software) from the OEM. These licenses can range from $10k to $700k for complex tools; and are the single greatest hurdle for customers of 3rd-party brokers. The consensus was that licenses are not unreasonable in principle, but customers really expect to receive some value in terms of software upgrades and service support for their payment. Service-contracts from OEMs certainly minimize the risk of working with used or refurbished tools, regardless of the seller.

Hallway discussions with equipment brokers revealed that they’re tracking a tremendous number of 200mm tools which are planned to be decommissioned over the next 1-2 years. How the industry will absorb these tools remains to be seen, but with SECS/GEM interfaces and modular sub-system designs, it’s likely that most of these tools will remain productive somewhere in the world.


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071012: Managing mature fabs

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Anonymous Ray Bunkofske said...

FDC is a proven contributor to the efficiency of the semiconductor manufacturing process. Modern FDC applications available from multiple suppliers provide a solid means to address the concerns mentioned in your Blog. Instead of making separate charts for every parameter, product and recipe combination it is much preferred to build multivariate models where the parameters are normalized in the background so as to greatly reduce the number of charts. There is no reason for more than two or three charts per tool-chamber combination to provide fault detection. Once a fault is detected then additional text or charts appropriate to the fault can be displayed to guide the resolution of the problem. Data analyzed in this way not only provides superior fault detection with virtually 0% false alarms, it enables prediction of several down stream metrics such as metrology results (film thickness, etch rate) and end of line electrical test results such as threshold voltage or overlap capacitance. Combine the signals from the tool with data from auxiliary sensors such as chamber impedance or full spectrum OES and you have a very powerful diagnostic and predictive tool. None of these capabilities are difficult to implement but they do require some care and preparation, something that could take six months to a year and it is difficult to get over this activation barrier. These efforts do not require huge investments in software, infrastructure or people, just a management with enough vision to stay the course and take advantage of the benefits as they materialize. Once through this phase of the program the system should pay back in 6-12 months through improved process capability and reduced time to detect.

Tue Oct 16, 09:29:00 AM PDT  

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.