Bookmark this Blog Subscribe to an RSS Feed of this Blog.
<< Home

080512: SAIL to fly
Ed’s Threads 080512
Musings by Ed Korczynski on May 12, 2008

SAIL to fly at 5 meters/min
The highlight of the April 16 North California Chapter of the American Vacuum Society’s (NCCAVS) Thin-Film Users Group (TFUG) meeting on printable electronics was the detailed technology presentation on self-aligned imprint lithography (SAIL) as developed by HP and PowerFilm Solar for their roll-to-roll (R2R) IC line. Many other companies are also developing real ultra-low-cost ICs and sensors using micron-scale printed thin-film transistors (TFT).

Palo Alto Research Center, Inc. (PARC, now independent from Xerox) working with Stanford University and Cabot Microelectronics recently won a DARPA contact to develop light-weight, inexpensive sensors using printing technologies. The basic technology uses printed TFT materials with all processing done at <200°C to allow for compatibility with plastic substrates, and should be applicable to the monitoring of pressure, acceleration, temperature, and chemical exposure.

PARC’s Ana Cladia Arias discussed methods used to deposit and integrate solution-processed materials using ink-jet printing. They have developed a complete additive process for the fabrication of simple prototype TFT backplanes on glass and on flexible plastic substrates. Surface energy control of the polymer gate dielectric layer allows printing of the metal source-drain contacts with gaps as small as 10μm. Silver nanoparticles are used in the ink that forms gate and data metals. The ION /IOFF ratio is ~105, and TFT mobility of 0.05 cm2/V·s were obtained.

Ink-jet printed electronics promise relatively low-cost manufacturing. Another highly customizable printing approach is the dip-pen technology developed by NanoInk for different applications. None of these technologies, though, could compete in cost and throughput with the rotating drum of a printing press, and so other companies are looking at ultra-low-cost patterning on roll-to-roll (R2R) substrates.

As mentioned in Tom Cheyney's recent flexible electronics article for SSTsister publication Small Times, Hewlett-Packard Laboratories (Palo Alto, CA) and PowerFilm Solar (Ames, IA) are working toward large-area arrays of TFTs on 330mm wide polymer substrates using exclusively R2R processes. Ohseung Kwon of HP Labs explained some details of the SAIL process which allows for 100nm feature alignment across a roll moving at >5 meters/min. Prototype work has been done

By encoding the geometry for all of the patterning steps into discrete heights of a 3D masking structure, the SAIL process borrows from the experiences of the MEMS industry in multilayer hardmask integration. All mask-formation is done before any etching, so that alignment is maintained regardless of process induced substrate distortion. Using a 100mm wide polyimide substrate (Kapton brand) for prototyping the UV-curable NIL process, they have achieved 4 imprint levels in 0.5μm step heights.

To form the TFTs, five blanket layers are deposited sequentially to form a stack, with no deposition temperature >260°C: PowerFilm had already developed PECVD for nitride and oxide as part of a-Si:H PV fab R&D for DARPA. HP Labs contributed their house-built R2R coater. The complex thin-film stack is as follows:
* Al gate metal,
* SiNx dielectric,
* a-Si semiconductor,
* n+ micro-crystalline-Si contact, and
* Cr top metal for source/drain.

Then the SAIL layer is formed, careful resist ashing allow for 3 or 4 layers with unique patterns to be exposed as masks. TFTs with on-off ratio >E7 (with dimensions 40μm × 2μm or 100μm × 1μm) have been printed.

The etching integration with this self-aligned mask is understandable challenging. Most are wet and use home-brew tooling, but some need to be dry plasmas. The wet etch system is 1/3 meter wide and can separate source/drain areas from gate areas at 1.5 meters/min. “If you can achieve the etch undercut very well, everything else can be done in a planar manner,” said Kwon regarding the complex multi-step etch flow.

R2R Plasma etching technology is challenging…to start with there is no “end-point” as commonly considered in wafer etching systems. Transferring the substrate from atmosphere to vacuum is achieved by load-locks for each roll that becomes sort of a batch. These are certainly not continuous processes. “Since we are using this kind of roll, once the surface is rolled up it serves as its own cleanroom,” explained Kwon.


Labels: , , , , , ,

posted by [email protected]
080512: SAIL to fly

Post a Comment


Post a Comment

<< Home

Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.