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070504: IBM add airgaps for faster chips
Ed’s Threads 070504
Musings by Ed Korczynski on May 04, 2007 (updated June 12, 2007 to correct details of the IBM airgap etch process, which had erroneously referred to the third-step being RIE, when it is wet as confirmed by both D. Edelstein and S. Nitta)

IBM adds airgaps for faster chips
Airgaps have long been considered as structures to increase the speed of on-chip IC interconnects, though no one had developed manufacturing-worthy process flows. Only in the last year have companies such as Philips (now NXP) shown overviews of likely airgap manufacturing processes, though without production commitments. Now IBM has invented a new variation on airgaps that uses a self-assembling polymer mask layer as part of the process flow, and claims this can be a simple drop-in addition that adds only ~1% to chip cost for each dielectric layer gapped. Thus for an advanced multilevel interconnect, a ~5% cost adder should provide 35% faster chips or 15% less power consumption.

Circuit speeds are limited by the dielectric constant (k) of the insulating material surrounding metal lines, so the industry's Roadmap has focused on ever lower k dielectric materials. Unfortunately, materials engineering for a new dielectric material is difficult and expensive, and despite tremendous efforts and many false-starts over the years, the entire world has now settled on SiCOH by CVD as the lone dielectric material (k~3) that provides acceptable cost, yield, and reliability. So-called ultralow-k (ULK, aka “extreme low-k”) films are merely k~3 SiCOH with the addition of ~20%-40% by volume of nanopores to reach k~2.4. More nanopores cannot be added without degrading yield and reliability, so the only practical way to get to k~2 is to incorporate a single large pore with clever processing as an “airgap.”

A multiyear development effort to create a manufacturable airgap process was led by IBM fellow Dan Edelstein, program manager for low-k CVD BEOL, who provided Solid State Technology and WaferNews with exclusive insight into how they achieved these remarkable results. He explained that unlike previously known airgap process flows, the IBM approach starts with a standard dual-damascene copper and SiCOH dielectric process that has been in production for years. Airgaps are formed using a multi-step etch, using a hardmask patterned with either self-assembling monolayers or standard lithography depending upon the geometry of the interconnect.

Unfortunately, IBM's press release touting the airgap achievement is so grossly hyped that it’s caused severe misunderstanding throughout most press reports on this process. The new technique "skips the masking and light-etching process,” says the official release. “Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it.”

In reality, while self-assembly can be used to make an array of nominally 20nm holes by spin-coating and baking, these holes merely pattern the hardmask that is used to etch the gaps into the dielectric, explained Edelstein. A non-critical lithography step is used to block out circuit areas that do not need gaps, he said. The self-assembly layer is not even used to pattern the hardmask used to make airgaps at upper levels of the interconnect. “At some point in the hierarchy it becomes more viable to use lithography instead of self-assembly,” he said.

While IBM doesn't use airgaps for the first level of metal, they could be used at any of the higher levels within the hierarchical interconnect stack, Edelstein noted. “Most chips won’t need air-gaps on all levels, but perhaps on half,” he said.

No matter the level, a special three-step etch process to form gaps with narrow top openings is the key to this process (see figure). “We etch a narrow channel down so it will cap off, then deliberately damage the dielectric and etch it so it looks like a balloon,” he explained. “You have a big gap with a drop in capacitance and then a small slot that gets pinched off.”

Starting with dual-damascene copper lines/vias and SiCOH single-phase dielectric, the essential IBM airgap process flow is as follows:

1) Deposit hardmask;
2) Spin-coat an imaging layer; either special new diblock polymer or standard photoresist;
3) Create holes using either the self-assembly properties of the diblock or standard lithography;
4) Block out circuit areas to not be etched using non-critical photolithography;
5) Transfer holes from the imaging layer to the hardmask;
6) Etch three-step sequence—first an anisotropic RIE to form deep openings into SiCOH, then plasma damage of the column sidewalls, then isotropic wet etch to remove most of the remaining SiCOH underneath the hardmask;
7) Strip hardmask; and
8) PECVD of the next SiCOH dielectric level to cap the gaps with a classic “pinch-off” shape.

Since the self-assembling mask layer is not aligned to the underlying interconnect structures, and since the block-out mask is “non-critical” to save costs, the hardmask will inevitably expose the tops and sides of some metal lines to RIE. Consequently, the SiCOH etch chemistry needs to have excellent selectivity so as to not attack copper and any metallic barrier layers. Edelstein says that they’ve been able to work with standard gas precursors for this critical RIE step.

The new airgap process is an optional loop off of the standard flow, so designers can choose to use airgaps at any of the levels in the on-chip interconnect hierarchy—and IBM also has developed an automated algorithm for making the block-out mask. “As a customer you can turn on the air-gap option for any level on any chip. We can put the gaps in independent of any incoming design,” Edelstein told WaferNEWS. The ability to add air-gaps as a “drop-in” to an existing on-chip interconnect process flow minimizes risks, and explains the company’s confidence that this flow will be used in manufacturing by 2009.

While the diblock polymer is only one part of this airgap process, it is a significant addition. Chemists at IBM Almaden Research reportedly developed this material for broad applications in fabs—it’s like a standard photoresist in terms of handling and dispensing, it has a wide process window, and IBM has detected no shelf-life problems for up to one year.

Using self-assembly in coordination with lithography opens up new possibilities in general for integrated process flows, so look for news of additional applications in coming years. “We hope that we can use directed self-assembly to get to other device features,” said Edelstein. “This is just the tip of the iceberg.”

— E.K.

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070504: IBM add airgaps for faster chips

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.