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070116: HP's crossbars pay three nodes early
Ed’s Threads 070116
Musings by Ed Korczynski on January 16, 2007

HP’s crossbars pay three nodes early
HP’s bet on 30 very smart people and modest lab space for a decade seems to have paid off early. R. Stanley Williams, senior fellow at HP Labs and founding director of the HP Quantum Science Research (QSR) group, has led this brain-trust since 1995. Nano crossbar arrays have been considered for far future memory and logic, but now they’re unveiled as a new 15nm-width field programmable nanowire interconnect (FPNI) circuit concept that may see production in 2010 along with 45nm node technology…three nodes earlier than anyone expected!

On a beautifully grey Winter Solstice day in Palo Alto, M. David Levenson (editor of MicroLithography World) and I joined SST senior technical editor Debra Vogler to meet Williams and his team and tour their lab. I saw enough evidence to support this three-node-jump claim for their nano crossbars. This novel circuit architecture appears to be both manufacturable and scalable, with what seem to be only two new unit processes: nano imprint lithography (NIL) for the bar formation, and the spin-on/etch of the molecular switching layer. Modeling of FPNI circuits show functionality with scaling down to 4.5nm-wide crossbars.

Team members Philip J. Kuekes, Shih-Yuan Wang, and Wei Wu provided us with a fantastic tell and show: discussion of crossbar architectures and fabrication processes, followed by a tour of the lab with the cool custom equipment. HP is one of the few large companies that still supports fundamental R&D for the industry, and the company creates multi-disciplinary teams comprised of systems/information theorists, circuit designers, physicists, chemists, and mechanical and materials engineers.

“One of the interesting things about HP is that it’s a big company that has re-invented itself,” commented QSR computer architect Kuekes. Teams continue to invent new device structures as well as research the processes, materials, and equipment necessary to form them. For example, there’s a trade-off between the manufacturing precision in the CMP step and the system design complexity to handle variability, and HP has all the brains needed to quantify trade-offs. “We have an amazing number of people from different disciplines,” said Kuekes. In the end, they had some physicists measure and model the physical platen in the CMP tool and then affix precise weights around the rim to “balance” it like a wheel on your car.

They also built their own NIL tool, and they are currently working on the 5th generation. Mask formation can be quite complex using MEMS-like processes to achieve special frequency doubling. Any NIL process and hardware IP will probably ultimately be licensed out, since HP isn’t in the equipment business. (David Lam was working on process control for plasma etching with HP the late 1970s, but HP did not want to get into the equipment business, so he left on good terms and then formed Lam Research.)

One of the great aspects of the crossbar design is that none of the manufacturing control has to be perfect—bars are expected to fail, and signal multiplexing through redundant lines compensates. Prior reports had indicated that 11 lines of a generic crossbar array could have 10% random failure and still guarantee 100% signal transmission of an 8-bit-wide multiplexed data stream. For FPNI circuit applications, HP’s models show that a crossbar array with 20% randomly failing lines should still provide 75% chip yield.

The bottom electrode is platinum, while the top electrode is platinum over titanium. Forming the cross connections between the orthogonally aligned top and bottom bars are molecular monolayers. The monolayer is blanket deposited over the patterned bottom electrodes, and then etched using the top electrodes as the mask. Each cross-junction is a resistive memory element within an array that can function as a memory or latched-logic circuit, or an FPNI.

Both electrodes are formed by lift-off lithography using dual-layer resist. “People do not know how to do platinum etch,” reminded QSR scientist Dr. Wu, “so we have to do a lift-off process.” The top “imaging layer” of resist is formed by NIL. E-beam direct writing with 60nm pitch is used for NIL mold fabrication, but some tricks allow doubling of the spatial frequency along with dual e-beam writing so that they can achieve 30nm pitch today. Then the bottom “transfer layer” resist is formed and undercut by sequential isotropic and anisotropic RIE. The undercut is essential so that the sidewalls are not coated by metal PVD, which allows for clean lift-off of the metal on top of the resist when the resist is stripped. “That’s how we can get crossbars with much higher yield,” commented Wu.

It’s worth noting that lift-off was a standard way to form metal interconnects back in the 1970s when linewidths were multiple microns. In all lift-off processes, the metal deposited between resist lines remains in place, while a wet solvent dissolves away the resist such that any metal on top just floats in the strip solution. This is a bit of an inherently messy situation, and stripper flow and filtering must be properly managed so that these bits of metal do not drop onto the wafer surface as defects. Still, with proper control of the resist to eliminate any sidewall deposition, lift-off patterning can be highly robust and manufacturable.

We don’t really know any of the details about the processing of the molecular monolayer, but we may suspect that its final form can sustain the temperatures used in standard packaging processes. Since the array is the top-most layer in the FPNI design, the monolayer need not be compatible with the 400-450°C standard used in the lower interconnect processing. Working FPNI chips aren’t expected for a year, and there are certainly many details to be resolved before the anticipated 2010 manufacturing debut of nano arrays. but the crossbar prototypes seen in the lab look good. I’d bet on it working.


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070116: HP's crossbars pay three nodes early

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.