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071102: Leti continues to lead research
Ed’s Threads 071102
Musings by Ed Korczynski on November 02, 2007

Leti continues to lead research
Leti (Laboratoire d’electronique et de technologie de l’information) is conceptually 1/3 of CEA (Commissariat a l’Energie Atomique), with nuclear energy and nuclear bombs the other major sections. The atomic reactors at the Grenoble site have been shut-down and now the entire sprawling campus is devoted to ~€300M annual micro-electronics work. The huge new Minatec fab is also on this site, and any developed technology that appears to be commercially viable will be spun out as a “baby” company; Leti has had over 30 babies so far, of which Soitec has grown up the most. Soitec and Leti still maintain close working relations, with personnel routinely spending one day each week at each others’ sites.

TraciT and PicoGiga were also Leti babies, though both have since been absorbed within Soitec. TraciT works on transferring finished device layers, using a combination of thinning with backgrinders/CMP and the Smart-Cut technique. “The Smart-Cut technique is a toolbox, not a single process,” explained Camille Darnaud-Dufour, VP of Communications for Soitec, who accompanied me on the Leti tour. Smart-cut—using hydrogen implant/anneal—works very well cutting layers up to 1μm thick, but to do 5-10μm you need some temporary bonding and wafer thinning. For the latter applications, Leti works with de-bondable SOI using handle-wafers and temporary adhesives.

Laurent Clavelier, who leads much of the work on new layer-transfer technologies such as wafer-to-wafer GeOI and InP chip-to-wafer heterogeneous integration, graciously took me on a full tour through the 200mm and 300mm fabs, which do both pure R&D and pilot production, with typically ~100 lots of wafers-in-process at any given time, running three shifts 24hrs/day during the week and half of the weekend. The fab is stuffed with standard production tools, such as Applied Materials’ implanters and CVD, ASM for epitaxial growth, Lam etchers, Semitool for ECD, Ebara for CMP, and KLA-Tencor and Veeco metrology tools.

In addition to standard CMOS fab tools, Leti has several unique tools such as a fully configured 200/300mm EVG bonder providing precise control of wafer-to-wafer alignment for work on patterned and device layer transfers. This system provides integrated single-wafer wet cleaning including a megasonic arm, and with control of bonding parameters it can perform automated designs-of-experiments. In addition to standard lithographic steppers, Leti uses e-beam direct-write with a single-beam for precise gate-length formation.

GeOI work now involves transferring not just blanket substrates, but full pMOS Ge FETs, which Clavelier claimed “is the best way to do fully depleted high-performance germanium on insulator.” Leti is also working on a “sequential front-end” process that would form nMOSFETs using strained SiGe as a first layer, and after planarization then compression bond a blanket 0.5μm thin <110> Ge layer on top. The pMOSFETs can then be formed in the transferred Ge layer since they require a maximum processing temperature of just 600°C.

GaNOI work is done in coordination with the PicoGiga people, using a combination of epitaxy and layer-transfer to aim for the highest-brightness blue LEDs. Work on optical interconnects continues for clock distribution on chip. Using indium phosphide (InP) III-V wafers to create laser diodes and detectors, thinned dice are bonded to wafers containing thin film optical waveguide structures.

Leti also pursues work on double-gate MOSFET to make high-power and low Vt devices such as 4T SRAMs. Doing so in planar structures requires the use of buried gates below transferred channel layers, so patterned layer transfer capability is enabling.

For 3D stacking applications, Leti and Minatec work with ST and the U. of Bologna on high-speed chip-to-chip communications through capacitive coupling across a silica bonding layer. Two CMOS wafers, each with nine layers of copper interconnects, can be bonded together face-to-face; one wafer is thinned, and then shallow bind-vias are formed to allow for wire-bonding down to exposed bond pads.

A very novel application of a blanket layer transfer that results in a pattern is controlled by a precise angular misalignment. A few degrees precise twist of a top wafer relative to a bottom wafer results in a crystalline mismatch that forms periodic dislocation strips. Using crystals with cubic orientations exposed on their faces can thus result in orthogonal arrays of dislocation strips with 50nm spacing, and these dislocations can be selectively etched to form orthogonal trench arrays for memory cells.

With so much exciting and ground-breaking work going on, it is a bit surprising that Leti is not more widely known for leading the industry -- though parent organization CEA is comparable to the US’ Sandia National Labs, and the culture of an organization devoted to creating weapons-of-mass-destruction is necessarily rather secretive. Even though Leti mostly pursues commercial technology development today, the legacy of secrecy continues as the default culture and the organization just doesn’t have the habit of self-promotion. Somewhat quietly then, Leti continues to lead.


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071102: Leti continues to lead research

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Anonymous Howard Levine said...


I had the opportunity to participate in last Summer's EMC3D roadshow that included a stop at Leti and was very impressed with the excellent facilities in this most beautiful town of Grenoble.

Howard Levine
SemiConn Consulting
Stamford, CT

Tue Nov 13, 02:31:00 PM PST  

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071026: Soitec catalyzes SOI consortium
Ed’s Threads 071026
Musings by Ed Korczynski on 26 October 2007

Soitec catalyzes SOI consortium
Earlier this month after the SEMICON Europa show, Soitec COO Pascal Mauberger, led me on a tour of the company’s two manufacturing and one R&D lines in Bernin, France across the creek from ST in Crolles. Soitec has taken a bit of a gamble on expanding capacity with a new line in Singapore, just when volumes for SOI wafers have publicly stalled. However, strong technical advantages should result in new demand for engineered substrates, and CEO André-Jacques Auberton-Hervé is now leading an industry consortium to catalyze chip-makers’ adoption of SOI.

The “chateau” built to house Soitec has the classic design element of a bridge over a moat, while the mirrored sides of the building reflect the awesome beauty of the French Alps. Inside the complex is the Class1 ballroom layout of Bernin1, the company’s first fab that is now capable of producing 800K/year on ≤200mm wafers. Connected by a walkway, Bernin2 is the company’s Class10-100 ballroom layout 300mm dedicated line (also 800K/year). An overhead transport was added two years ago to increase output to handle the increased demand for all the latest-generation game consoles and AMD’s microprocessor ramp in Dresden. Though PS3 sales have been weak, Xbox and Wii game platform sales have been strong, and all use SOI chips.

Both Bernin1 and Bernin2, as well as the new 300mm line announced for Singapore, use completely standard industry tools from established OEMs to do the specialty implants and thermal treatments needed for their layer transfer process. Among the setup are TEL furnaces, Applied Materials implanters, EVG bonders (a bit customized at 300mm, instead of the standard 200mm size used in MEMS fabs), Mattson and Applied Materials RTP, and KLA-Tencor metrology tools. Over 1000 Soitec employees are running these lines 24/7 and essentially 365 day/year.

Bernin3, a stone’s throw from Bernin2, was built originally by MEMSCAP as its own fab. Essentially just a shell when it was acquired by Soitec in mid-2006, it now has three 500 m2 cleanrooms doing R&D on III-V materials such as Nanosmart GaN development, and complex pattern transfers. Transferring already patterned layers (not blanket layers) was work originally started at LETI, spun out as TraciT Technologies and then acquired by Soitec; the first product was imagers using backside illumination. Bernin3 runs 100mm, 125mm, and 150mm wafers, so the R&D tool set is flexible to handle any of these wafer sizes. If any device captures serious demand, then pilot production could occur with dedicated tools in the (currently empty) fourth space in the fab shell. Including its PicoGiga division's work on MBE epitaxy for GaN, Soitec has a lot of IP and know-how to bring to the development of high-efficiency and high-brightness LED production.

Soitec keeps only a handful of finished goods inventory on site, since the company is completely integrated into a just-in-time integrated supply-chain. Soitec maintains at least one month’s of inventory at each customer site, maintaining ownership until each wafer enters the IC fab line. Likewise, three suppliers maintain starting wafer inventory at Soitec, only “delivering” the wafers when they enter the SOI production line.

Auberton-Hervé, Soitec CEO and newly elected chairman of the SOI Industry Consortium, is modest about Soitec’s role in bringing the possibility of cost-effective SOI manufacturing to the semiconductor industry over the last decade. “We were a bit of the catalyst, but the demand was from the ecosystem,” he claims. The consortium in current form did grow out of periodic SOI user workshops Soitec had sponsored, and Auberton-Hervé notes that interactions between device researchers during a September 2006 workshop led to the demand for the creation of an open ecosystem.

To be sure, the proprietary IBM-ecosystem has had SOI design-flows, design IP, and appropriately tuned manufacturing processes for lease for many years. Yet not every company has been willing or able to work with the folks in East Fishkill, NY, and so this new consortium may really open up a new avenue to add value for many companies.

“The value of the consortium is in the ability to accelerate innovation,” said Auberton-Hervé. “We have to be more efficient in how we bring value to the whole food-chain. Roadmaps for cost in each segment will help, but it’s more global than that.” Most people think that finFETs really call for SOI, and both represent huge power-savings for portable battery-powered applications. From first-principles it seems that SOI has advantages for mixed-signal isolation. Embedded memory using ZRAM structures (license to Innovative Silicon) is also an attractive option.

With Auberton-Hervé committed to “doing well by doing good” in leading this consortium for the industry as well as for his company and shareholders, much more of the industry may end up using SOI. It may help with functional integration at 45nm and beyond, and that may help double battery life for next-generation iPods and e-Phones. SOI and other layer-transfer technologies will almost certainly become increasingly useful as simple x-y scaling inevitably slows, and Mauberger will be coordinating the operations of global Soitec fabs to keep the wafers flowing around the world.


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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.