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071026: Soitec catalyzes SOI consortium
Ed’s Threads 071026
Musings by Ed Korczynski on 26 October 2007

Soitec catalyzes SOI consortium
Earlier this month after the SEMICON Europa show, Soitec COO Pascal Mauberger, led me on a tour of the company’s two manufacturing and one R&D lines in Bernin, France across the creek from ST in Crolles. Soitec has taken a bit of a gamble on expanding capacity with a new line in Singapore, just when volumes for SOI wafers have publicly stalled. However, strong technical advantages should result in new demand for engineered substrates, and CEO André-Jacques Auberton-Hervé is now leading an industry consortium to catalyze chip-makers’ adoption of SOI.

The “chateau” built to house Soitec has the classic design element of a bridge over a moat, while the mirrored sides of the building reflect the awesome beauty of the French Alps. Inside the complex is the Class1 ballroom layout of Bernin1, the company’s first fab that is now capable of producing 800K/year on ≤200mm wafers. Connected by a walkway, Bernin2 is the company’s Class10-100 ballroom layout 300mm dedicated line (also 800K/year). An overhead transport was added two years ago to increase output to handle the increased demand for all the latest-generation game consoles and AMD’s microprocessor ramp in Dresden. Though PS3 sales have been weak, Xbox and Wii game platform sales have been strong, and all use SOI chips.

Both Bernin1 and Bernin2, as well as the new 300mm line announced for Singapore, use completely standard industry tools from established OEMs to do the specialty implants and thermal treatments needed for their layer transfer process. Among the setup are TEL furnaces, Applied Materials implanters, EVG bonders (a bit customized at 300mm, instead of the standard 200mm size used in MEMS fabs), Mattson and Applied Materials RTP, and KLA-Tencor metrology tools. Over 1000 Soitec employees are running these lines 24/7 and essentially 365 day/year.

Bernin3, a stone’s throw from Bernin2, was built originally by MEMSCAP as its own fab. Essentially just a shell when it was acquired by Soitec in mid-2006, it now has three 500 m2 cleanrooms doing R&D on III-V materials such as Nanosmart GaN development, and complex pattern transfers. Transferring already patterned layers (not blanket layers) was work originally started at LETI, spun out as TraciT Technologies and then acquired by Soitec; the first product was imagers using backside illumination. Bernin3 runs 100mm, 125mm, and 150mm wafers, so the R&D tool set is flexible to handle any of these wafer sizes. If any device captures serious demand, then pilot production could occur with dedicated tools in the (currently empty) fourth space in the fab shell. Including its PicoGiga division's work on MBE epitaxy for GaN, Soitec has a lot of IP and know-how to bring to the development of high-efficiency and high-brightness LED production.

Soitec keeps only a handful of finished goods inventory on site, since the company is completely integrated into a just-in-time integrated supply-chain. Soitec maintains at least one month’s of inventory at each customer site, maintaining ownership until each wafer enters the IC fab line. Likewise, three suppliers maintain starting wafer inventory at Soitec, only “delivering” the wafers when they enter the SOI production line.

Auberton-Hervé, Soitec CEO and newly elected chairman of the SOI Industry Consortium, is modest about Soitec’s role in bringing the possibility of cost-effective SOI manufacturing to the semiconductor industry over the last decade. “We were a bit of the catalyst, but the demand was from the ecosystem,” he claims. The consortium in current form did grow out of periodic SOI user workshops Soitec had sponsored, and Auberton-Hervé notes that interactions between device researchers during a September 2006 workshop led to the demand for the creation of an open ecosystem.

To be sure, the proprietary IBM-ecosystem has had SOI design-flows, design IP, and appropriately tuned manufacturing processes for lease for many years. Yet not every company has been willing or able to work with the folks in East Fishkill, NY, and so this new consortium may really open up a new avenue to add value for many companies.

“The value of the consortium is in the ability to accelerate innovation,” said Auberton-Hervé. “We have to be more efficient in how we bring value to the whole food-chain. Roadmaps for cost in each segment will help, but it’s more global than that.” Most people think that finFETs really call for SOI, and both represent huge power-savings for portable battery-powered applications. From first-principles it seems that SOI has advantages for mixed-signal isolation. Embedded memory using ZRAM structures (license to Innovative Silicon) is also an attractive option.

With Auberton-Hervé committed to “doing well by doing good” in leading this consortium for the industry as well as for his company and shareholders, much more of the industry may end up using SOI. It may help with functional integration at 45nm and beyond, and that may help double battery life for next-generation iPods and e-Phones. SOI and other layer-transfer technologies will almost certainly become increasingly useful as simple x-y scaling inevitably slows, and Mauberger will be coordinating the operations of global Soitec fabs to keep the wafers flowing around the world.


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071026: Soitec catalyzes SOI consortium

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.