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080121: SMC highlights PV, LED, and packaging materials
Ed’s Threads
Musings by Ed Korczynski on January 21, 2008

[Happy Birthday, Martin Luther King, Jr.!]

SMC highlights PV, LED, and packaging materials
Last week saw hundreds of microelectronics industry executives gather at ISS and SMC. The conventional forecasts for semiconductor manufacturing equipment and materials have been covered by previous WaferNEWS stories. SMC showed truly amazing perspective on new electronic materials markets of gigantic scales like photo-voltaics, high-efficiency lighting, and advanced 3D and WLP packages.

Solar is hotter than the sun these days, and Craig Hunter of Applied Materials provided a great overview of the whole market and his company’s leading position in offering turn-key fabs. The photo shows an Applied Materials’ SunFab PECVD 5.7 and those really are full size people standing next to a multi-chamber deposition system for PV on huge glass panels.

The global market in 2007 for PV panels was reportedly 4.8 GW, up ~50% from 2006. The current approximate cost to install a rooftop solar PV system is US$0.25-0.30/kWhr (absent incentives). However, nearly all PV manufacturers show near-term roadmaps to cut PV fab costs in half, and there are additional innovations possible in installation of modules, so it seems likely that price could drop to US$0.10-0.12/kWhr for large scale installations without any incentives. With demand forecasted to be extremely elastic to price, and with total global energy use growing at 2%/year on the scale of TeraWatts, PV will likely remain <1%>

The future of mega-fabs for PV panels includes integrated supply-chain campuses like the classic old Ford Rouge Plant in the 1920s. The thin-film PV fab of the future will be more efficient when if has a dedicated float glass plant for the substrate, a line for the thin-film encapsulant formation, and even packaging of the junction-boxes for the final modules. Each of these may be owned by a different company, but for economies of scale and manufacturing efficiency they’ll be adjacent to each other. Process gases such as hydrogen, silane, etc. account for ~17% of final panel costs, so long-considered innovations such as silane reclamation make be used in manufacturing In general it seems that the main scientific breakthroughs in PV have been made, and now the best engineers will win the race to fab profits. “People ask me all the time where I would locate a PV fab if I had to chose,” opined Hunter. “I think there’s a big opportunity for someone to put a factory in New Mexico, Arizona, or Texas.”

George Craford, CTO of Philips Lumileds Lighting Company, discussed the immanent “Revolution in lighting, high power LED technology.” As a demonstration, Buckingham Palace has been externally lit by LEDs at a cost of US$0.45/hr. The theoretical light output limit for an LED is 300 lumens/Watt, but the best in production is ~100 lumens/W, with 150 lumens/W on a roadmap. The plan is for high-power LEDs to be 1-3 per replacement bulb.

From the 1960s through the 1990s the LED brightness evolved at a fairly constant rate, though this was based on driving the same size chips with the same power. Starting ~10 years ago, the industry began to work with new packages to allow driving higher current-densities and resulting higher outputs for applications include automotive, flashlights, and projectors.

Why aren’t white LEDs everywhere? Quite simply the cost has been too high. For the same 1000 lumens output (60-100W incandescent bulb equivalent) the indandescent bulb costs $0.40, fluorescent tube $0.60, compact fluorescent $2, and white LED $10. Lumileds researchers seem confident that they can improve the basic Internal Quantum Efficiency (IQE) from ~45% today to ~90% tomorrow, and with higher drive current (700 mA to 2A) and lower chip and packaging costs the cost could be ~$1.

The energy savings with LEDs is truly impressive:

1000 lumens Input Power Energy cost/yr COO for 5 yrs
Incandescent 60W $48 $240
Fluorescent 20W $18 $90
Comp.Fluor. 14W $13 $85
White LED 6W $5 $26

Control of manufacturing is a concern since the variation in blue wavelength crossed with the yellow phosphor materials distribution creates variation in the color of white. The human eye is sensitive to subtle color variations and tight matching is needed for LEDs in the same room. Off-grid applications can be valuable using a single LED with a solar array or a bicycle generator…for example Light Up The World foundation has been installing LEDs around the world to allow children to be able to study schoolwork at night. China estimates that by changing to LED lighting it will save them as much electricity as the maximum planned output of the Three Gorges Dam. “They are going to dominate conventional illumination, it’s only a matter of time,” said Craford.

Packaging technology for ICs continues a steady evolution, with few examples more telling than the wirebonder. Wirebonders have periodically been considered as limited, but they evolve and now can go to 5 or even 8 levels of silicon useing new materials for dielectrics and interposers. FlipChip—which has been used almost exclusively for MCUs—is finally moving into the mainstream in combination with wirebonding and leadframes to allow for many efficient high-volume packages.. But SIP and SOC will continue to coexist in many possible variations using flipchip and wirebonding. PoP approaches also remain competitive, with variations using thinned silicon, recessed-cavities, and fan-in routing.


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071217: Post-FET future discussed at IEDM

Ed’s Threads 071217
Musings by Ed Korczynski on December 17, 2007

Post-FET future discussed at IEDM
Silicon-based CMOS FETs will still be used in commercial ICs in twenty years, but it’s likely that completely new devices will also be in production. It seems highly likely that nMOS and pMOS FET “switches” will be used for mainstream logic and memory until 2015-2020, when such things as cross-bar architectures and quantum diodes may be needed. This is the group opinion of the world’s leading IC fab researchers, as discussed in a 2007 IEDM evening panel discussion moderated by Prof. Dimitri Antoniadis of MIT: “Looking Beyond Silicon -- A Pipe Dream or the Inevitable Next Step?”

The industry will reach the practical limits of scaling planar bulk CMOS at different nodes for high-power logic, low-operating power logic, low stand-by power (LSTP) logic, and memory applications. “Transistor pitch scaling will be increasingly difficult due to stronger impact of parasitics and less effective stress engineering. Even if we can do it, power might limit what can be exploited," opined Wilfried Haensch of IBM. Vertical scaling may be required to minimize parasitic capacitance, and high-mobility channel materials must provide the same or better density scaling potential as silicon devices to be attractive. Inherent variability in sub-22nm node devices will be daunting: pattern variation, random discrete dopants, the number of charges per unit device, and interface roughness (poly grain boundaries, high-k morphology, impurity scattering, etc.).

As an example of tough near-term scaling limits, for a physical gate length of 22nm (effective length 16nm), IBM saw that the extrinsic switching time depended upon the current flux through narrow raised source/drain (S/D) regions, with relatively faster switching in short and wide S/D. “There is no new switch in site,” declared Haensch. “All candidates are either non-manufacturable or they can not be wired up.” Lacking a replacement to the silicon FET, system performance will continue to increase with respect to historical trends due to architectural solutions -- i.e., we’ll have systems with many ‘light-weight’ task-specific cores.

Akira Toriumi of the U. of Tokyo gave his educated opinion -- based on first principles of manufacturing he learned at Toshiba -- as to the best directions to go for a post-silicon future. He thinks that silicon microelectronics research will end in 2015, but any new materials, processing, and devices should be simple. “A one-dimension device like a wire, I don’t believe will be a solution; finFET will be a good candidate,” he said. He also advocates the use of germanium instead of compound semiconductors for new channels. “People are talking about Ge for pMOS and III-V for nMOS," he noted, "but why don’t we challenge Ge CMOS? We can get metal S/D Ge nFETs.” For scaling we need to consider not just channel materials but also contact materials for these new channels.

We are now in a world using digital computing solutions that is "very safe and reassuring,” said Jean-Philippe Bourgoin of CEA-LETI. “If we look back at the work of von Neumann and Turing they had to understand the theory much more than we do now.” Audience member Paolo Gargini of Intel interjected that according to the theory of Heisenberg’s Uncertainty principle, Intel’s planned FET scaling will be limited in the year 2020. A member of Gargini’s research group mentioned the crossbar architecture under development in Stan Williams’ Lab at HP as a likely eventual replacement for the FET. (See my Jan. 16, 2007 Ed's Thread for cross-bar architecture and processing details, based on a late 2006 tour of the lab.)

The next afternoon (Session 34, "CMOS Devices -- Advanced Device Structures"), the far limits of CMOS FET technology were shown by Samsung as experimental results of uniaxially strained {110} silicon nanowire transistor (SNWT) channels using an embedded SiGe Source/Drain for greatly improved pMOS performance. Starting with either SOI or bulk silicon wafers, they first grow embedded SiGe (20-40nm thick) and then Si. After hardmask patterning and a clever sequence of etching, the bottom of the grown Si {110} has become SNW floating above the removed SiGe, but the SiGe beneath the S/D remain, and the inherent SiGe/Si lattice-mismatch compressively stresses SNW to provide 1534μA/μm for pMOS. They saw nFET performance only ~15% lower regardless of {110} or {100} orientation, so good overall CMOS results are obtainable using {110}.

Beyond FETs and cross-bar architectures lies a technology concept still mostly disbelieved by the mainstream: quantum electronics. The IEDM plenary session included a talk by Hiroyuki Sakaki, from the Toyota Technological Institute at the U. of Tokyo, on “Roles of Quantum Nanostructures on the Evolution and Future Advances of Electronic and Photonic Devices.” By controlling the electrons within nanoscale layered structures, quantum confinement results in effective two-dimensional electrons and the ability to form devices such as resonant tunneling diodes, quantum wire FETs, quantum dot lasers, and planar superlattice FETs.

However, commercial quantum electronics still remains out in the future. Use of carbon nanotubes (CNT) grown from catalyst particles shows promise, “but it has been very difficult to control the site selection, as well as other parameters,” according to Sakaki. Charge storage phenomena in quantum dots using either Si or InAs appear like the most likely near-term applications. Though if this is merely an extension of flash memory cell technology, does it really count as “quantum electronics?”

In 20 years, will we see a non-FET-based computer? The aggregate opinion seemed to be “yes,” but don’t expect people in the industry who have lived with it forever to be able to think “outside the FET” and develop something revolutionary.

-- E.K.

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.