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080222: TSV forecast for millions of wafers
Ed’s Threads 080222
Musings by Ed Korczynski on February 22, 2008

TSV forecast for millions of wafers
Through-silicon vias (TSV) can be used to connect 3D multi-chip module stacks with improved performance and reduced timing delays. A new report by analysts at TechSearch International, Through Silicon Via Technology: The Ultimate Market for 3D Interconnect, provides a forecast for millions of silicon wafers to be made with TSV in the year 2014. For the next few years, however, it is likely that image-sensors and memory chip stacks will be the major high-volume applications, building on the estimated less than 50,000 wafers to be fabbed with TSV this year according to TechSearch President Jan Vardaman.

The industry is now moving past the feasibility (R&D) phase for TSV technology and into the commercialization phase, where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Global research organizations are looking at applications for TSVs including image sensors, flash, DRAM, microprocessors, FPGAs, and power amplifiers.

There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. In particular, as confirmed by Vardaman, if there are only 2 silicon layers to be assembled it is generally more cost-effective today to use flip-chip with wire-bonders. Another 1 or 2 chip layers can be easily added to the bottom side of an interposer, still without the need for TSV.

In so doing, the wire-bonds are not in any way limits on system performance, since flip-chip bumps and re-distribution layers (RDL) are still used to route signals from chip to chip within the package. Intel has announced that its newest 45nm microprocessor chip is the first to use a thick copper RDL layer along with a polymer interconnect dielectric (presumably spun-on). A thinned memory cache chip with metal bumps (presumably C4NP or equivalent) can then be flipped onto the microprocessor and lead-free connections re-flowed to the RDL for low-latency electrical interconnects. Wire bonds then connect the stack to the package pins through an interposer.

An interposer today is commonly built-up using thin-film laminates, but there is renewed interest in the use of silicon as interposers…which would require TSV. Many companies, including MEMS foundries and equipment suppliers, today offer foundry services to create silicon interposers containing TSVs. Silicon is a wonderful material to use as an interposer between silicon chips: same coefficient of thermal expansion eliminates shear stresses on bumps due to heating, excellent relative thermal conductivity to help heat leave the chips, and excellent mechanical strength. The only problem has been the cost compared to build-up laminates. If costs can be reduced, then demand should be very elastic for silicon interposers with TSV, and we could see interposers instead of product wafers as the main near-term market for silicon TSV outside of memory stacks.

Image sensors for camera modules are already in volume production, with major investments by Tessera and Micron in wafer-level-packaging TSV manufacturing technology. The next volume application seems to be memory stacks, but it is only high-cost niche IC applications today that can justify the added cost of TSVs over wire-bonds. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, though progress is being made.

Flip-chip was first introduced by IBM in the late 1960s, and it took approximately 40 years for the technology to become dominant such that more silicon wafers end up flipped instead of wirebonded today. TSV technology is already in use, but it will probably be decades before the majority of chips use it as a solution to the cost/performance trade-off challenge. The official semiconductor silicon wafer demand forecast is for ~10 billion of silicon by the year 2010, which corresponds to ~200 million silicon wafers (in 200mm wafer equivalents) to be fabbed. It is unlikely that more than a few million of them will need internal TSV, but if costs can be reduced it is possible that many more could use silicon interposers with TSV.


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080222: TSV forecast for millions of wafers

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.