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070323: Integration extends 193nm litho
Ed’s Threads 070323
Musings by Ed Korczynski on March 23, 2007

Integration extends 193nm litho
As thoroughly reported by WaferNews, SST, and Microlithography World, the 2007 SPIE lithography meeting detailed that 193nm wavelength lithographic reduction steppers may be the last mainstream lithographic technology for the semiconductor manufacturing industry. Whether dry or with the wafer under immersion (193i) of a fluid to push the resolution, there really is no other choice besides direct-write. Consequently, process development engineers now look for ways to create ever smaller device features using 193nm litho with clever combinations of other known unit-process steps: thin-film depositions, etches, and plasma surface treatments.

Double-exposure (in which a single resist stack is exposed twice) and double-patterning (with at least one thin-film hard mask, and usually two exposures) with 193nm are now in use and under development in different CMOS fabs. Double- and triple-patterning has been used in the MEMS industry for over 20 years, to allow for all lithography to be completed before complex multi-step etching of physical structures such as membranes and cantilevers.

A classic and well-known integration trick to extend litho is “resist-trim.” Used for gate formation, resist lines defined by lithography are plasma etched to thin them and so achieve linewidths below the resolution of the optics. Various resist-swelling techniques can narrow contact holes below lithographic resolution limits. Applied Materials now claims an anisotropic plasma etch of a hardmask can narrow holes.

Applied Materials now also touts two different hardmask materials: a dielectric advanced patterning film (APF) for most applications, and a 25-30nm thick PVD titanium nitride (TiN) film for integration with low-k dielectrics having porosity of up to 30%. The $2-$3/wafer APF has the amazing ability to “heal” line-edge roughness (LER) from an upper resist layer. Because it is not built out of large molecules like resist, the byproducts of etching the APF are small ligands with sp3 hybrid bonds that coat exposed sidewalls with diamond-like carbon, which preferentially fills in 1-2nm features. Consequently, LER of 2.5 nm in resist becomes just 1.5 nm when etched into the APF.

Applied Materials has developed a complex, self-aligned double-patterning scheme that uses a quadruple-hardmask and a self-aligned spacer nitride with a single litho step:
- Depositing a blanket stack of APF + oxide + APF + nitride on top of poly,
- Coat resist and dry 193nm litho of pattern into resist,
- Trim resist, then etch pattern into nitride and top APF,
- Deposit self-aligned sidewall spacer nitride,
- Etch APF, and then
- Etch poly gate features using remaining spacer nitride.

Improved metrology will certainly be essential to manage any of this new integration. Metrology now controls the process—it doesn’t merely monitor—and it must also provide the vital data to build design and litho models. For example, building an OPC model requires accurate metrology to capture the interdependencies between the mask, resist, and at least one etch. Thus, SPIE now includes thorough sessions on DFM and metrology.

The history of semiconductor manufacturing technology is the history of risk-avoidance at the bleeding-edge of human knowledge. “The industry is overall conservative as any manufacturing industry must be,” commented TI’s Hans Stork in his keynote address at SPIE this year. “We only move to a new material or a new approach if there is no alternative.”

Technologies must hit the sweet spot in the middle of capability/risk/cost, and it’s the overall integrated process that counts. If multiple low-risk and inexpensive process steps can replace a single risky and overall more expensive step, then the reduced cost and risk of the multi-step flow will always be worth the longer fab cycle-time.


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070323: Integration extends 193nm litho

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.