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070427: Life after CMOS commoditization
Ed’s Threads 070427
Musings by Ed Korczynski on April 27, 2007

Planning for life after CMOS
It’s hard to feel upbeat about the future of mainstream semiconductor manufacturing after attending this year’s SEMI Strategic Business Conference in Napa, CA, where presentations detailed the end of the good times. After decades of leading the world in high-tech value-adding, the IC business is now mature and just another part of the global electronics industry. This is nice enough, unless you remember the record revenues, profits, and capital equipment expenditure levels of the 1990s.

Trends within the IC industry indicate that the average cost to develop a new IC product has risen from $10M at the 90nm node to $50M at 65nm. With a targeted 10x return on research and devleopment over the life of the product, you need to see over $500M in chip sales for a single 65nm product. Remembering that consumer chips typically sell for $5 each in quantity, that means before even starting a new 65nm chip design you need to show demand for 100M units, which will effectively lock out a number of applications spaces, noted Wil Josquin, VP of strategy and innovation for NXP Semiconductors.

In his concluding keynote presentation, Art Zafiropoulo, CEO of Ultratech, included a slide from Freescale showing the percent of investment into a final IC product going toward packaging has gone from <20%>50% in the last five years. His final slide ended with the final line reading that advanced packaging will be the only differentiating technology. Amkor’s David Hays, VP of business development, wafer level processing, reminded the audience that, “There’s no way to get all the features and functions in cell phones that we all want using old chips and old packages.” For example, Motorola’s trend-setting V3 RaZR handset includes six chip-scale packages (CSP) plus 14 wafer-level packages (WLP).

Despite providing substantial value, outsourced semiconductor assembly and test (OSAT) providers such as Amkor or STATS/ChipPac find it difficult to make a profit. “The industry doesn’t want to pay us to do the work we do,” Hays lamented. “It’s like Walmart -- they’ll say what they’re willing to pay for it, and it’s up to you to figure out a way to make a profit.” There are seemingly no more obvious and easy solutions available. If you do a silicon chip shrink from 90nm to 65nm nodes for cost savings, you may find that the added packaging cost to handle a smaller chip with tighter pitches negates any saving in the silicon.

Consumerization drives rapid electronic product life cycles that stress the supply chain. Scott DeBoer, Micron’s director of process development, reminds us that commodity pricing can be very volatile —e.g., NAND flash spot prices averaged $9.50 on Dec. 1, but had sunk to $5.15 by Jan. 26. Extremely tight coordination is required between EDA, IP, fab, packaging, and ATE partners to have any hope of first silicon right. Plus, after decades of evolution, nanometer-scale CMOS logic technology has reached commoditization, such that the chip itself just doesn’t make the product any longer. Future added-value will come from software and advanced packages and bundled-internet-subscriber-services, not from the ICs which power it all.

With Intel sending 90nm logic technology to China, and TI stopping CMOS development at 45nm, the writing is clearly on the wall. Mike Thompson, manufacturing operations GM for STMicroelectronics, did the math for why TI said no more, concluding that process technology spending as a % of development is being squeezed out by increasing efforts in software development for new products in the ASIC/ASSP world. With ~$400M required to develop a new silicon process technology, if this is 20% of the total research and development budget which is capped at 20% of total sales, then only IDMs with >$10B IC revenue can maintain independence in silicon process technology development. For logic technology, the world is settling down to just three or four independent sources of mainstream CMOS technology development: Intel, the IBM ecosystem, the foundries, and Japan.

IBM continues to lead the industry in technology innovation as the center of the collection of partners in the Common Platform Alliance (CPA). This alliance includes many design and packaging members who add value beyond the limits of silicon, such as Amkor, ARM, Analog Bits, Blaze, Chipidea, Clear Shape, Cadence, Magma, Mentor Graphics, Ponte, Synopsys, and Virage Logic. The industry continues to innovate using current business models, though we should expect to see many shake ups below the first-tier of IDMs, OEMs, and OSATs.

Major IDMs will continue to manufacture in-house, though they will both provide and use more and more foundry services. Fabless companies will continue to function as they have in recent years, with clear distinctions between the top-tier and all others. Medium-size IDMs will partner to remain “fast-followers.” If you’re supplying equipment or materials to leading-edge fabs, expect that greater purchasing power will consolidate into fewer hands. Overall what can we expect from the new reality of CMOS logic commoditization? Keep up the good work, and you might even get paid some day.

— E.K.

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070427: Life after CMOS commoditization

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.