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080429: SAFC Hitech opens modular scalable plant
Ed’s Threads 080429
Musings by Ed Korczynski on April 29, 2008

SAFC Hitech opens modular scalable plant
A trusted supplier of specialty materials for semiconductor manufacturing must have great safety, control, and smarts. These specialty chemicals include precursors for growth and deposition, photoresist and slurry additives, as well as CMP, ECD, encapsulation, packaging and assembly, fuel cell, PV, and energy storage materials. Custom molecules must be specially design, assembled, refined, and packaged, and each step requires expert knowledge.

Part of Sigma-Aldrich, SAFC Hitech raked in >$70M of sales in 2007, ~$40M of which came from the Epichem business it acquired in February 2007. Epichem had established a unique business proposition as a total supply chain partner to compound semiconductor manufacturers, yet lacked the resources and expertise to scale up to silicon manufacturing scales.

SAFC has plenty of manufacturing scale, and now even more so with the $9M investment into a new production plant in beautiful Sheboygan, WI. Each plant is multipurpose and reconfigurable by design, with room for expansion depending upon demand. As a result, SAFC Hitech is uniquely positioned to be able to supply specialty materials on annual scales of hundreds of kilos to a few tons.

SAFC distillation columns in one safety-isolated “cell” in the new Sheboygan, WI specialty materials manufacturing plant. (Source: SAFC)

The facility has been designed with deep experience in the best practices of specialty chemicals production. Each “cell” in the facility (see Figure) is designed and constructed to ensure safety in setting up flexible capacity to purify highly toxic and reactive chemistries. A concrete cell is roughly the footprint of a standard trade-show booth (~10m2) with >5m ceilings to allow for tall columns. All potential spark sources are removed from each cell. Production manager James Bilitz noted that a bucket of alcohol could be thrown on the floor and it would not ignite.

The filling, packaging, and analysis facility was custom-designed from the ground up to ensure purity in packaging of ampules and tanks. Several innovative techniques eliminate as many sources of metallic contamination as possible: walls and ceilings formed from welded PVC, a custom vacuum oven to dry containers, and sophisticated purge/fill systems inside of custom UHPA hoods. A state-of-the-art mass-spectrometer is used to confirm that individual metal contamination levels are kept in the sub-parts-per-trillion range.

SAFC expects the construction and operational experiences learned with the new Sheboygan facility will provide a blueprint for future expansion in overseas markets, particularly in China and South Korea.

Geoff Irvine, SAFC Hitech's commercial development and marketing director, explained that chemical innovation will be needed more and more to allow the industry to move forward. “We have people in the CMP space and ARC space coming to us asking us to make specialty materials,’ he said, adding that the company also does “a lot of private label manufacturing.” Services offered range from molecular design to process development optimization/scale up and commercial manufacturing; analysis; raw material sourcing and characterization; and even things like vendor audits, hazard evaluation, packaging design, and regulatory filings.

Complex molecules can be toxic, explosive, unstable, and generally very tricky to work with when breaking them down in use, and it’s all more difficult when building them up through chemical synthesis pathways. Also, a molecule that breaks down in shipping or storage tends to form particles. ALD processes use highly reactive chemistries that instantly degrade if exposed to oxygen or water vapor, for example, so extremes of environmental control are needed in the chemical engineering of ALD precursors. “We go to great lengths to create wonderfully complex molecules which our customers destroy as soon as they get them,” quipped Peter Heys, SAFC Hitech R&D director and former head of Epichem.

The company is central to the semiconductor manufacturing industry with customers in precursor R&D as well as large-scale production, but if pressed to name just one core competency, “it’s our ability to handle difficult materials,” proclaimed SAFC president Frank Wicks. “For example, our high-potency materials have to be manufactured in glove boxes. People generally don’t like to work with these materials and that’s good for us.” It’s good for the whole industry that SAFC likes to do this ever more essential work.


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071211: HK+MG real details shown at IEDM

Ed’s Threads 071211
Musings by Ed Korczynski on December 11, 2007

It’s time for IEDM, and ~1600 leaders of the CMOS fab world have gathered in Washington D.C. to announce the latest, greatest in new devices. The first big news concerns high-k/metal-gate (HK+MG) transistors for 45nm node and beyond processing. With many parallel sessions covering the most important technology trends in IC manufacturing, it is impossible to mention all of the great results presented by teams from around the world (apologies to: ST/NXP/Freescale, Fujitusu, MIRAI, NEC, SELETE, Sony, Toshiba, and TSMC).

Presenting on behalf of 53 co-authors, Intel VP Kaizad Mistry disclosed some real details of the company’s latest 45nm process technology featuring HK+MG. Finally answering the gate-first or gate last question with “both,” Intel has decided that the tough integration challenges for high performance logic can be best met with HK first but MG last processing. The transistors feature 1.0nm equivalent oxide thickness (EOT) dielectric, based on an atomic layer deposition (ALD) of a hafnium-based compound -- no additional details yet on other elements likely to be used in this ALD step, whether the phase of the final material is amorphous or crystalline, or what is the specific interface from the HK to the highly-strained channel. (In a side conversation after Mistry's talk, Intel Fellow Tahir Ghani confirmed the need for this interface, but would provide no details, only noting that it is critical for mobility.) pMOS performance is improved by increasing the Ge content of the embedded SiGe to 30% (from 23% @ 65nm, and 17% @ 90nm) and by reducing SiGe proximity to the channel. Lithography utilizes 193nm dry patterning, though some masks require two exposures in two resist layers along with a sacrificial hardmask. Transistors feature 35nm physical gate length, ultra-shallow junctions, and nickel silicide. Drive currents are benchmarked at 1.0V, a low 100nA/μm IOFF and at 160nm contacted gate pitch. pMOS drive current of 1.07 mA/μm (51% improvement over 65nm), while nMOS drive current is 1.36mA/μm (12% better than 65nm). SRAM arrays with cell sizes of 0.346μm2 and 0.383μm2 (performance dependent) and multiple microprocessors are already in volume production, with claimed excellent yields.

Figure. TEM micrograph of 45nm Intel high-k + metal gate pMOS transistor. (Source: IEDM2007 10.2)

Intel’s gate-first/last HK+MG process flow for 45nm transistors is as follows:
- STI, well, and VT implants,
- ALD (18-20Å) of HK gate dielectric,
- Polysilicon deposition and gate patterning,
- Source/drain extensions, spacer, Si recess and SiGe deposition,
- Source/drain anneal, Ni salicidation, ILD0 deposition,
- Poly opening CMP, poly removal,
- pMOS work-function metal deposition,
- Metal gate patterning, nMOS work-function metal deposition, and
- Metal gate Al fill and Al CMP, etch-stop layer deposition.

IMEC and its partners (TSMC, Matsushita, Infineon, Samsung, and NXP) showed a low VT CMOS gate-first HK+MG using TaC-based metals and laser-only annealing. Symmetric low VT values of ±0.25V and unstrained IDSAT of 1035/500μmA/μm (for nMOS/pMOS respectively) at IOFF=100nA/μm and VDD=1.1V were demonstrated on a single wafer. To do so required Hf-based high-k dielectric capping layers of lanthanum oxide (La2O3) for nMOS and aluminum oxide (Al2O3) for pMOS to lower EOT from ~17 to ~15 while maintaining the same target VT. HK-caps in combination with a laser-only activation anneal maintain band-edge equivalent work-function (EWF) and minimal EOT re-growth. La2O3 thickness control allows for VT turning from 0.2 to 0.6 for nMOS. HfSiO shows lower VT and higher mobilities compared to HfSiON. The laser-only anneal further results in improved LG scaling of 15nm and a 2Å TINV reduction over the spike reference. Lam etchers were used for gate patterning. IMEC has also been working on HK+MG for finFETs.

Prof. A. Toriumi et al. (U. of Tokyo, MIRAI-AIST, MIRAI-ASET) presented on “Materials Science-based device performance engineering for metal gate high-k CMOS.” EOT is based on k, which is based on the internal field and the polarizability of the material itself. HfO2 has monoclinic phase, but adding lanthanum, silicon, yttrium, and/or titanium can change the phase to cubic or tetragonal, while the k increases to ~30. Adding La2O3 increases the crystallization temperature up to 800-1000°C (over the range of 20%-40% incorporation), and the amorphous phase has the best overall properties. Regardless of composition, leakage current depends only on the physical thickness, which shows that the leakage mechanism is pure direct tunneling. Thus, using higher-k films with equal EOT (down to ~0.5nm) significantly reduces the leakage. Flat-band voltage shift has been clearly shown to be determined only by the dipoles formed at the bottom interface between SiO2 and HK, and not by the HK to MG interface. Scattering effects should be correlated to both the material itself and oxygen vacancies in the material.

Important information is being learned about nMOS/pMOS boundaries, according to H. Rusty Harris from SEMATECH, who gave an amazing presentation on a “Flexible, simplified CMOS using HK+MG on Si(110). “What we have shown is that if we add capping layers on top of the dielectric we do not see mobility degradation,” he said. Carrier mobilities depend upon crystallographic orientation, and changing from standard (100) to (110) orientation allows for mobility increase of 3X for holes, while electron mobility drop by ~1/2. Mixed orientation -- Si(100) for nMOS, and Si(11) for pMOS -- has been examined but process complexity, cost, and variability seem unattractive. Data for Si(110) planar CMOS is relatively similar to multiple orientation approach (with much lower manufacturing cost), though an pre-amorphosizing implant is used to minimize diffusion which is faster in (110) compared to (100) silicon. Even better results should be seen with finFETs, which inherently require orientation engineering. Using large 0.25μm planar transistor lengths (not short enough to fully realize the nMOS improvements), they showed that ring oscillators were nearly equivalent regardless of (110) or (100). Sub-threshold leakage is an important factor in LSTP optimization, and gate-induced drain lowering (GIDL) is the second biggest factor in off-state power. Without even optimizing the process flow for (110), using (110) lowered GIDL by an order of magnitude compared to (100).

CEA-LETI-MINATEC/Soitec use TiN metal over HfO2 HK gate dielectric to explore the limits of HK+MG with SOI substrates. From a historical perspective, Takagi et al. (IEDM '97) showed that long-channel transport conditions effectively degrade electron mobility as dielectric thickness decreases. Gate lengths from 18nm to 10μm were fabricated, all with widths of 10μm, EOT 1.7nm, and 145nm BOX thickness. They consider ballistic carriers may primarily determine the conduction in sSOI short-channel devices, and invoke a “ballisticity rate” to partly explain the influence of surface roughness scattering. Si thickness down to 2.5nm for SOI has been used for both HP (IOn=780&MU;MA/μm) and LP (IOFF=10pA/μm) devices.

Meanwhile, IBM and its partners missed out on getting a HK+MG paper into IEDM this year, and instead issued a press release about 32nm development. Having publicly committed to gate-first processing, Freescale researchers in the alliance have published a paper in the Journal of Applied Physics on the crystalline phases formed using zirconium along with hafnium-oxide. Hafnium zirconate (HfZrO4) alloy gate dielectric and hafnium dioxide (HfO2) films were formed by atomic layer deposition using metal halides and heavy water as precursors.


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posted by [email protected]
071211: HK+MG real details shown at IEDM

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Anonymous L. Chan said...

Hi Ed,

Great IEDM summary of the latest HK/MG development.

L. Chan

Wed Dec 12, 02:18:00 AM PST  

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070720: HK+MG metrology technology
Ed’s Threads 070720
Musings by Ed Korczynski on July 20, 2007

HK+MG metrology technology
With High-k (HK) dielectrics and metal-gates (MG) now being ramped into CMOS production at Intel and IBM, much of the excitement at the just finished SEMICON West 2007 in San Francisco centered around manufacturing technologies needed for these new materials. ASM and Imago sponsored seminars on these topics, and much of the discussion in panel discussions sponsored by Praxair and DuPont centered on the challenges of working with these new materials. In particular, setting up affordable in-line metrology for these new ultra-thin materials will be tricky.

Recently departed SEMATECH Fellow Alain Diebold, now a Professor at the U. Albany, provided an overview of the need for HK metrology in a breakfast seminar sponsored by Imago. For HfxSi1-xO2, both x=0.25 and 0.75 are stable structures, which may be regarded as Hf substituted in an SiO2 matrix and Si substituted in an HfO2 matrix, respectively. HK layers in production will likely be just 3-5 atomic layers thick. Since improving hole mobility is inherently difficult, one first possible application of finFETs is to integrate PMOS finFETs with planar nFETs at the beginning of the 32nm node. “We need atom-by-atom characterization and metrology for fins in R&D; today, not later,” informed Diebold.

The U. of North Texas—previously renowned for its jazz music scholarships—inherited an old TI fab and received $11M in funding to invest in cutting-edge metrology tools. TEM can resolve sub-angstroms spatially, but chemical resolution is limited to ~1%. Secondary ion mass spectroscopy (SIMS) provides sub-parts-per-million chemical resolution, but lacks special resolution. Local-electrode atomic probe (LEAP) systems sold by Imago Scientific Instruments provide ~2Å spatial resolution and ~E18 chemical resolution, using full-width-half-maximum (WFHM) measurements of a calculated concentration curves to calculate thickness. Approximately 80nm diameter silicon samples are cut from wafers using a dual-beam FIB, and 6-7 samples can be prepared in an hour by a skilled FIB operator. Dopant “snow-plow” effects in diffusion, quantum well structures, and buried interface roughness can all be analyzed to calibrate in-line metrology techniques. LEAP reconstructions of this HK stack as-deposited and post-anneal show 0.5nm of Hf and O diffusion.

Since LEAP provides excellent resolution but is inherently destructive and relatively slow, it is ideal for R&D; but cannot be used for in-line production control. Still, LEAP and other lab techniques are vital for calibration of production control approaches. “The type of information that you get from R&D helps you set up your in-line metrology, and the two work hand-in-glove, as Howard Huff used to say,” reminded Diebold. With HKMG now ramping in production, there’s a crop of new in-line metrology tools available.

ReVera provides XPS tools that can resolve thickness, composition, profile, and chemical bonding states information from thin dielectric films, and claims customers are using the tool to measure gate-dielectrics and HK storage for memory chips. XPS can measure all elements heavier than He for any film or material up to 100Å thick in any part of the process flow.

After one year of promoting it for high-volume metrology applications such as HK+MG, Metryx claims sales have doubled for its mass monitoring tool, which has sufficient resolution to detect differences in the atomic masses between silicon (28 g/mole) and hafnium (178 g/mole) in hafnium-silicate ALD layers. The company claims wins with customers for process control applications in volume fabs, typically measuring the masses of >60 wafers/hr.

Metrosol’s vacuum ultra-violet (VUV) spectroscopic reflectometer was designed specifically to handle in-line metrology of ultra-thin dielectrics. Two manually-loaded chambers have been in use for over two years at customers, one for hafnium-silicon-oxide films and one for nano-imprint lithography (NIL). The first five beta units of the fully-automated tool will be ready this September. The purchase cost is claimed to be 1/2 to 2/3 of an x-ray or extended range ellipsometer, and typical throughputs are 2x-10x of such systems. (Click for WaferNEWS' interview with CEO Kevin Fahey.)

Since thin-film metrology is pointless if you can’t deposit the material in the first place, the readiness of the industry to begin volume production of chips using HK gate-stacks has been shown by ASM officially releasing its Pulsar ALD chamber for the company’s Polygon cluster-tool. ASM likes to term its ALD variant atomic-layer CVD (ALCVD), though the process and hardware seem quite similar to other single-wafer ALD technologies.

Gate-first HK stacks use a capping layer such as lanthanum-oxide to form a dielectric dipole in the vertical dimension. This cap oxide is hygroscopic, so the stack should be formed without breaking vacuum to eliminate exposure to water vapor. This is just one of the critical integration issues which must be controlled in the formation of HK+MG CMOS transistors. With atomically thin films and complex interdependencies in integration, the “make versus buy” decision for 2nd-tier fabs will almost certainly fall to buying it, because it just cannot be easily made. “Even if you reverse-engineer the chip, you can’t discern the integration scheme,” explained Glen Wilk, product manager for transistor products at ASM.

Don’t worry if all of this sounds almost too difficult to manage. Professional materials scientists have been working on the research for decades, and we’re now in the era of engineering specific solutions to known problems. Stay tuned for yearly breakthroughs.


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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.