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071211: HK+MG real details shown at IEDM

Ed’s Threads 071211
Musings by Ed Korczynski on December 11, 2007

It’s time for IEDM, and ~1600 leaders of the CMOS fab world have gathered in Washington D.C. to announce the latest, greatest in new devices. The first big news concerns high-k/metal-gate (HK+MG) transistors for 45nm node and beyond processing. With many parallel sessions covering the most important technology trends in IC manufacturing, it is impossible to mention all of the great results presented by teams from around the world (apologies to: ST/NXP/Freescale, Fujitusu, MIRAI, NEC, SELETE, Sony, Toshiba, and TSMC).

Presenting on behalf of 53 co-authors, Intel VP Kaizad Mistry disclosed some real details of the company’s latest 45nm process technology featuring HK+MG. Finally answering the gate-first or gate last question with “both,” Intel has decided that the tough integration challenges for high performance logic can be best met with HK first but MG last processing. The transistors feature 1.0nm equivalent oxide thickness (EOT) dielectric, based on an atomic layer deposition (ALD) of a hafnium-based compound -- no additional details yet on other elements likely to be used in this ALD step, whether the phase of the final material is amorphous or crystalline, or what is the specific interface from the HK to the highly-strained channel. (In a side conversation after Mistry's talk, Intel Fellow Tahir Ghani confirmed the need for this interface, but would provide no details, only noting that it is critical for mobility.) pMOS performance is improved by increasing the Ge content of the embedded SiGe to 30% (from 23% @ 65nm, and 17% @ 90nm) and by reducing SiGe proximity to the channel. Lithography utilizes 193nm dry patterning, though some masks require two exposures in two resist layers along with a sacrificial hardmask. Transistors feature 35nm physical gate length, ultra-shallow junctions, and nickel silicide. Drive currents are benchmarked at 1.0V, a low 100nA/μm IOFF and at 160nm contacted gate pitch. pMOS drive current of 1.07 mA/μm (51% improvement over 65nm), while nMOS drive current is 1.36mA/μm (12% better than 65nm). SRAM arrays with cell sizes of 0.346μm2 and 0.383μm2 (performance dependent) and multiple microprocessors are already in volume production, with claimed excellent yields.

Figure. TEM micrograph of 45nm Intel high-k + metal gate pMOS transistor. (Source: IEDM2007 10.2)

Intel’s gate-first/last HK+MG process flow for 45nm transistors is as follows:
- STI, well, and VT implants,
- ALD (18-20Å) of HK gate dielectric,
- Polysilicon deposition and gate patterning,
- Source/drain extensions, spacer, Si recess and SiGe deposition,
- Source/drain anneal, Ni salicidation, ILD0 deposition,
- Poly opening CMP, poly removal,
- pMOS work-function metal deposition,
- Metal gate patterning, nMOS work-function metal deposition, and
- Metal gate Al fill and Al CMP, etch-stop layer deposition.

IMEC and its partners (TSMC, Matsushita, Infineon, Samsung, and NXP) showed a low VT CMOS gate-first HK+MG using TaC-based metals and laser-only annealing. Symmetric low VT values of ±0.25V and unstrained IDSAT of 1035/500μmA/μm (for nMOS/pMOS respectively) at IOFF=100nA/μm and VDD=1.1V were demonstrated on a single wafer. To do so required Hf-based high-k dielectric capping layers of lanthanum oxide (La2O3) for nMOS and aluminum oxide (Al2O3) for pMOS to lower EOT from ~17 to ~15 while maintaining the same target VT. HK-caps in combination with a laser-only activation anneal maintain band-edge equivalent work-function (EWF) and minimal EOT re-growth. La2O3 thickness control allows for VT turning from 0.2 to 0.6 for nMOS. HfSiO shows lower VT and higher mobilities compared to HfSiON. The laser-only anneal further results in improved LG scaling of 15nm and a 2Å TINV reduction over the spike reference. Lam etchers were used for gate patterning. IMEC has also been working on HK+MG for finFETs.

Prof. A. Toriumi et al. (U. of Tokyo, MIRAI-AIST, MIRAI-ASET) presented on “Materials Science-based device performance engineering for metal gate high-k CMOS.” EOT is based on k, which is based on the internal field and the polarizability of the material itself. HfO2 has monoclinic phase, but adding lanthanum, silicon, yttrium, and/or titanium can change the phase to cubic or tetragonal, while the k increases to ~30. Adding La2O3 increases the crystallization temperature up to 800-1000°C (over the range of 20%-40% incorporation), and the amorphous phase has the best overall properties. Regardless of composition, leakage current depends only on the physical thickness, which shows that the leakage mechanism is pure direct tunneling. Thus, using higher-k films with equal EOT (down to ~0.5nm) significantly reduces the leakage. Flat-band voltage shift has been clearly shown to be determined only by the dipoles formed at the bottom interface between SiO2 and HK, and not by the HK to MG interface. Scattering effects should be correlated to both the material itself and oxygen vacancies in the material.

Important information is being learned about nMOS/pMOS boundaries, according to H. Rusty Harris from SEMATECH, who gave an amazing presentation on a “Flexible, simplified CMOS using HK+MG on Si(110). “What we have shown is that if we add capping layers on top of the dielectric we do not see mobility degradation,” he said. Carrier mobilities depend upon crystallographic orientation, and changing from standard (100) to (110) orientation allows for mobility increase of 3X for holes, while electron mobility drop by ~1/2. Mixed orientation -- Si(100) for nMOS, and Si(11) for pMOS -- has been examined but process complexity, cost, and variability seem unattractive. Data for Si(110) planar CMOS is relatively similar to multiple orientation approach (with much lower manufacturing cost), though an pre-amorphosizing implant is used to minimize diffusion which is faster in (110) compared to (100) silicon. Even better results should be seen with finFETs, which inherently require orientation engineering. Using large 0.25μm planar transistor lengths (not short enough to fully realize the nMOS improvements), they showed that ring oscillators were nearly equivalent regardless of (110) or (100). Sub-threshold leakage is an important factor in LSTP optimization, and gate-induced drain lowering (GIDL) is the second biggest factor in off-state power. Without even optimizing the process flow for (110), using (110) lowered GIDL by an order of magnitude compared to (100).

CEA-LETI-MINATEC/Soitec use TiN metal over HfO2 HK gate dielectric to explore the limits of HK+MG with SOI substrates. From a historical perspective, Takagi et al. (IEDM '97) showed that long-channel transport conditions effectively degrade electron mobility as dielectric thickness decreases. Gate lengths from 18nm to 10μm were fabricated, all with widths of 10μm, EOT 1.7nm, and 145nm BOX thickness. They consider ballistic carriers may primarily determine the conduction in sSOI short-channel devices, and invoke a “ballisticity rate” to partly explain the influence of surface roughness scattering. Si thickness down to 2.5nm for SOI has been used for both HP (IOn=780&MU;MA/μm) and LP (IOFF=10pA/μm) devices.

Meanwhile, IBM and its partners missed out on getting a HK+MG paper into IEDM this year, and instead issued a press release about 32nm development. Having publicly committed to gate-first processing, Freescale researchers in the alliance have published a paper in the Journal of Applied Physics on the crystalline phases formed using zirconium along with hafnium-oxide. Hafnium zirconate (HfZrO4) alloy gate dielectric and hafnium dioxide (HfO2) films were formed by atomic layer deposition using metal halides and heavy water as precursors.


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posted by [email protected]
071211: HK+MG real details shown at IEDM

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Anonymous L. Chan said...

Hi Ed,

Great IEDM summary of the latest HK/MG development.

L. Chan

Wed Dec 12, 02:18:00 AM PST  

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070824: Intel finds signs of heterogeneous life after silicon
Ed’s Threads 070824
Musings by Ed Korczynski on August 24, 2007

Intel finds signs of heterogeneous life after silicon
With CMOS circuits using silicon channels running into performance limitations, doping with germanium and straining the lattice have already been used to push the limits. The limits of silicon remain, though, and so compound semiconductors are again under consideration as building blocks for mainstream ICs—this time integrated on top of 300mm silicon wafers.

The first solid-state transistors were built with germanium (Ge), but Ge crystals do not grow a nice surface-passivating oxide as do silicon crystals, and the oxide is vital to prevent surface defects that would otherwise kill performance. Grown silicon oxide has been the heart of cost-effective high-volume IC production for over 40 years. Even high-k (HK) gate dielectrics based on hafnium-oxides will typically be used on top of a grown and partially etched-back silicon oxide layer.

What comes after high-k and metal-gates (HK+MG)? Heterogeneous integration of compound semiconductors will completely replace the silicon channel. Silicon wafers would still be used, but only as physical supports for different NMOS and PMOS transistor materials. The new channel materials will be deposited and/or grown using technologies such as metal-organic CVD (MOCVD), solid-phase epitaxy (SPE), and spike/flash anneals.

Though HK+MG has been spun as the biggest change in 40 years, when compound semiconductors are integrated with silicon it will be a far greater integration challenge for it will require an even greater number of new materials. Now Intel researchers have reported passing a milestone along the road many travel to heterogeneous integration: integrated superior device performance.

This summer, Intel researchers achieved success at fabricating high performance devices using both indium antimony (InSb) and indium gallium arsenide (InGaAs) channels, and in each case they perform as well as their counterparts on GaAs wafers. On their internal blog, they show curves for the performance of both types of devices, with individual transistors both higher performing and consuming less power than equivalently sized silicon devices.

Mike Mayberry, Intel’s director of components research, has articulated five general areas of research and develop needed to create a competitive commercial heterogeneous semiconductor fab technology:
1) put compound semiconductors on silicon wafers,
2) find different high-k dielectrics for the gates,
3) develop PMOS materials to go with known NMOS,
4) develop enhancement-mode devices instead of depletion-mode, and
5) “Make them small enough to compete with silicon transistor densities.”

The last is the tricky part. These circuits are conceived of as being possible at or past the 22nm node, so that means high-yielding dense 32nm and likely 22nm CMOS circuits will already be in production using strained SiGe. Heterogeneous circuits will have to compete with Si/SiGe chips on price, so transistor packing density will be crucial.

By the time InSb and InGaAs could be integrated on silicon wafers, finFETs should also be options along with planar transistor structures. In an email exchange with me after his initial blog posting, Mayberry answered some questions relating to finFETs as possible structures for heterogeneous integration. “It is possible that in the timeframe we’re discussing that trigate structures could be a strong candidate and thus, that builds pressure to find a vertical solution for III-V,” he confirmed, but he admitted that, “we do not as yet have a solution to that problem.”

If finFETs are used, new metal alloys will need to be developed to be able to form minimal resistance electrical contacts to these new materials. Even if planar structures are used, the contacts will almost certainly be to the channel material instead of silicon to avoid the need for a >5nm transition zone from material to material that would otherwise limit packing density. Due to the need for this transition layer in planar devices with silicon contacts, and the performance advantages to a reduced number of boundary layers, it seems likely that metal contacts will be direct to the new compound semiconductor materials.

In my email exchange with Mayberry, he confirmed only that “we have not decided how to make electrical contact for those future devices.” One thing he knows—and will let us know—is that for Intel’s current work, SOI would just get in the way and everything is grown on bulk silicon wafers.

This is all starting to get into some serious materials engineering. Mayberry’s blog pre-announces that they will show enhancement-mode device results using these materials at IEDM this December. Since these newest devices will be “normally off” they should result in minimal leakage and reduced power-consumption for circuits. We can almost certainly expect unexpected subtle second-order integration challenges with all of these new materials, with the semiconductor industry now moving into “interesting times.”


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070824: Intel finds signs of heterogeneous life after silicon

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Blogger Raouf said...

Why the In2O3 compound are not used in the new heteregeneous devices ?
Raouf Bennaceur

Wed Aug 29, 02:19:00 AM PDT  
Blogger Raouf said...

Why the In2O3 componds are not used in the new intel device

Wed Aug 29, 02:22:00 AM PDT  

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070622: Intel researches teraflops and biochips
Ed’s Threads 070622
Musings by Ed Korczynski on June 22, 2007

Intel researches teraflops and biochips
Andrew Chien, Intel VP and director of research, provided an exclusive interview with Solid State Technology and WaferNEWS during Intel Research Day this year. Chien heads all Intel research, involving nearly 1000 people at 15 locations worldwide (three of which are at universities). “There are nearly a hundred people doing research, and nearly a thousand people doing platforms based on the research,” explained Chien. “It’s not device physics or materials science, it’s real manufacturing work.” You can now find more information at [email protected] Blog.

Chien is responsible for thinking of new microprocessors, new microprocessor applications (including those embedded), and novel fab-able devices that could retain high profit margins. Discussing novel non-silicon transistor technologies, such as printable or polymer electronics, Chien expressed that these newer technologies must find winning applications beyond what is currently served by silicon chips.

Opportunities exist in the intersection of digital CMOS fabrication technology and biological applications. Intel's Fab8 in Israel has been working on novel sensor architectures based on field-effect devices on 200mm wafers, where the quantity of specific molecules bonded to uniquely tuned sites creates a change in current flow. Think of this as similar to sticking a sensor layer to the top gate of a FET where the change in bonded molecules alters the current flow through the channel. Integration of sensor elements with CMOS circuitry in a hybrid-SoC is expected to be easily done on-chip; while sensors could be integrated with separate CMOS chips in 3D stacks, there is already sufficient “free silicon real estate” at the periphery of the sensor areas to fit in all the CMOS needed.

Intel is also trying a super-computer architecture end-run on IBM’s Blue Gene, by releasing a Teraflop multicore single chip. On display at the Research Day event was a rack with a board stuffed with very fancy metal packaging and active water-cooling loops surrounding a (reportedly) 275mm2 160-core chip in 65nm technology. This chip has been shown to perform at 1.01 teraflops @ 0.95V, 62W based on the following single-chip architecture:
1 poly, 8 Cu metal lines form a 2D mesh,
100 million transistors with dynamic power management,
80 tiles (3mm2 each) composed of dual FPMAC cores, and
Packaged with 1248 pins (343 signal) C4 and a 14 layer PCB.
Memory hierarchy for this new chip design includes private L1 memory within each core, as well as several levels of shared L2 cache. A third level of SRAM or DRAM cells will likely be integrated as a separate chip in a 3D stack to manage bandwidth requirement in integration to the overall system.

What a bunch of teraflop chips is very good at is anything “computationally intensive,” requiring extreme amounts of computing power -- for example, calculating the interacting and overlapping phases of light shifted by randomly placed sub-wavelength features across a vast 2D space, a.k.a. inverse-lithography maskmaking (see related writeup by phase-shift mask pioneer and MicroLithography World editor M. David Levenson). Yan Borodovsky and Vivek Singh showed a mask with pits etched to greater depth for longer wavelength red, so that a common laser-pointer shone through the mask would form a bit of an Intel logo on the wall. You almost have to see this hologram-like effect to believe it yourself. There is no metal to mask the light, just the phase cancellation from the pits. The fundamental capability of computationally intensive inverse lithography modeling will be key to all of Intel’s design- for manufacturing (DFM) going forward, even if the phase-pit masks enabled by the technology aren’t anticipated until <32nm.

Beyond manufacturing, Intel also researches software breakthroughs that might demand a lot of processing power. “We shifted resources to respond to the increased focus upon ‘context-dependent computing,’ where sensor data is processed to determine whether you’re eating, sleeping, or watching a performance,” explained Chien. “We can already determine human emotion based on facial gestures, and that information will be incorporated into context-dependent devices.”

With a teraflop possible from a single chip, the capabilities seem nearly endless. Ten years ago, Gordon Moore foresaw that once the atomic limits of manufacturing are reached (still a bit off, but now quite on the horizon), we’ll be in a realm of hundreds of millions of really inexpensive transistors, and clever designs will break open whole new applications for silicon chips. Chien confirms that the design mindset today does not consider the number of transistors to be a constraint, merely the inherent power consumption of those working and waiting. With clock-rates now somewhat fixed, Chien says that it’s actually much easier to work with innovation at the architectural level.

Hold on to your hats, folks—now that designer have to do more than just scaling and clock-accelerations to get performance increases, they might actually start pulling their own weight, and this industry will really take off!


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070525: Intel-IBM fab hype-war and truths
Ed’s Threads 070525
Musings by Ed Korczynski on May 25, 2007

Intel-IBM fab hype-war and truths
It has been said that the first casualty of war is the truth…even more so in a hype-war. An interview appearing on a popular electronics industry Web site is the most recent battlefield in this ongoing hype-war between the world’s semiconductor manufacturing heavyweights. As tradeoffs in fab technology become more fundamental at 45nm nodes and beyond, different companies choose to deploy similar technologies in different ways. The truth is inherently complex and thus a bit complex to describe, and can die under the assault of hype.

Among fundamental choices today we find the following: double-patterned dry or single-patterned wet lithography for critical layer patterning, and use of porous or airgap low-k dielectric for on-chip multi-level interconnects. Intel has chosen double-patterned dry lithography and non-airgap low-k dielectrics. IBM has chosen single-patterned wet-lithography and airgap dielectrics.

As shown by Hoofman,, in the pages of SST last year, there are many different airgap process flows, which can produce many different airgap structures. Airgaps may be complete or partial between lines, and this is one of the more fundamental parameters to consider in integrating the structures into real chips. Thus, airgap1 is not airgap2 (General Semantics suggests the use of “indexing” to remind us of the essential distinctions between members of any conceptual set).

Using “complete airgap” flows and removing all dielectric between lines to achieve the absolute minimum capacitance does indeed create the two general problems articulated by Mark Bohr in the recorded interview: an expensive critical-lithography mask to ensure proper via landings, and copper electromigration sensitivity. However, the IBM flow uses airgaps only in the middle of line spaces while leaving dielectric material on the sidewalls of copper lines.

The IBM airgap process exposes parts of some metal sidewalls during the tricky three-stage gap etch, but the subsequent dielectric CVD process re-coats the exposed sidewall areas prior to “pinching off” the tops of gaps. With adequate sidewall dielectric in place, via landing and electromigration issues can be minimized if not avoided. Intel’s Bohr certainly understands airgap integration issues far better than I do, but because he’s not in a position to comment on how his competitor’s process might work, he accurately and properly expressed Intel’s results in the interview, and the generic disadvantages of approaches not currently taken by Intel.

However, a statement summarizing the interview reads thusly: “Mark Bohr, Intel senior fellow, says his company looked at air-gap technology like IBM recently introduced, and dismissed it as costly and inefficient.” That's a misinterpretation. The truth is that Intel never panned IBM’s airgap technology—Bohr answered a specific question about IBM’s technology with a generic answer about non-IBM technology. Of course, Bohr can very reasonably say that he has no knowledge if IBM’s technology beyond what is muddied in the official press release. Since IBM’s marketing spun the technology truth to the point of grandiose hype, it provides easy opportunity for Intel to comment on the hype instead of the truth. (Incidentally, further information on the general concept of self-assembled nanotechnology for lithographic masking applications can be found in the most recent issue of Microlithography World.)

The IBM hype was that no new lithography is needed. Intel counters that a generic process flow for airgaps requires critical-lithography steps. The truth is that the IBM flow does use an additional lithography step for each airgap level, but it’s non-critical and the mask generation has been automated as a button in the EDA deck. Critical-lithography steps for 45nm node processing can be 10X more expensive than non-critical patterning steps. If the IBM airgap process required critical lithography for each level then it might add 20%-25% to the cost of each chip, but with non-critical lithography it might add only 5%-8%.

For most people in the world who lack experience in fab processes, subtle complexities get lost in translation and details are distorted or lost. The truth about nanometer-era fab processes is that they are all tough to develop with inherent integration trade-offs. With Intel and IBM now going down divergent paths, it’s truly difficult to assess a fab technology “leader” in anything but hype.

— E.K.

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Anonymous Dan Edelstein said...

We (IBM) have been wrongly portrayed as having chosen a different path, i.e. of airgaps instead of low-k or ultralow-k, and that we have “diverged.” (also wrong in implied added cost, mask/litho needs and criticality, and other pot-shots). In fact we were quite surprised at this misinterpretation - that concept was never stated by us nor meant to be implied. It's especially surprising given all the leading low-k and ultralow-k progress we have published and put into production. We are simply adding airgaps to our arsenal - as an option on top of a low-k baseline technology - not at the expense of the low-k insulator used in the baseline build to be gapped. Also please note there is no comparison between the wiring capacitances. Our airgap approach drops any given wiring capacitance by ~35%, regardless of how low the "k". Most chips would not require all levels to be gapped, if any. We think our high-end server CPU's will benefit the most.
For references on our leading low-k roadmap (which is lower-k than Intel's at each node), please refer to our 45-nm announcement at IEDM 2006, and prior papers on 90-nm and 65-nm at IITC 2004, IITC 2005, and AMC 2006. We are continuing our low-k reduction path, as our alliance partners, vendors, and customers know. We intend to keep pushing along the leading edge of low-k BEOL, and that in turn is underpinned by noteworthy experience developing those low-k materials, as well as understanding root causes for Cu reliability.
Airgaps are positioned on top of that baseline, reducing k by ~35% for just ~1% additional wafer cost per level gapped (and yes indeed, the added lithography is noncritical, and we didn't hold back in specifying that - it appeared in your first article, as well as Microprocessor Report May 21 and several others who published our process flow).
So to sum up, our airgap approach is a low-cost/high-performance option, selectable by chip and by wiring level, and fabricated on a competitive low-k BEOL baseline. The issue is not either/or, i.e. either gaps or low-k. It is simply whether one has this gapped option to offer, or not.

Tue Jun 12, 06:38:00 PM PDT  

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070129: Intel wins race to be Intel
Ed’s Threads 070129

Musings by Ed Korczynski on January 29, 2007

Intel wins race to be Intel
How did it happen? How could Intel present 45nm transistor results with high-k dielectrics and dual metal gates (HK+MG) years ahead of everyone else? Mark Bohr, Intel senior fellow in logic technology development, stated, “I don’t believe any other company will have high-k and metal gates until the 32nm node or later.” If this is true, it is only because IBM and other companies felt that they wouldn’t need HKMG for 45nm so they did not start manufacturing work two years ago. Thus, Intel has won a very difficult race as the single contestant.

It seems that the company even surprised itself with these results. On Thursday Jan. 25th, the day before the official announcement, Intel invited journalists to a last-minute show-and-tell at its Robert Noyce HQ building in Santa Clara, CA. PCs running on 45nm “Penryn” chips were shown—all of which came from the “first-silicon” wafer with these new materials processed using the first mask-set. Packaged first-silicon chips received at Intel’s Folsom test lab at 1:00 am had functioned, and the team immediately rushed one into a motherboard which promptly booted a software OS two hours later. Intel showed a photo of the team toasting their success with Martinelli’s sparkling cider at 3:00 am—give Intel credit for maintaining entrepreneurial zeal with nearly 100,000 people.

Two core competencies were at work to get to these results: extreme discipline in manufacturing execution, and proprietary design and yield-learning methodologies. Since Intel has always had to live in the brutal merchant market, it has always aimed for the sweet spot in the middle of manufacturing-cost and chip-performance, and then relentlessly driven to meet its goals. Instead of silicon-on-insulator (SOI), Intel pushed traditional planar transistors on bulk silicon wafers to the limits of traditional materials for its current 65nm node manufacturing.

Looking at 45nm options about two years ago, Intel decided to stick with bulk silicon wafers and add HK+MG. In Jan 2006 it announced yielding SRAM TEG chips with >1B transistors, but kept secret that these chips used HK+MG. Still secret is the hafnium-based dielectric composition, both of the metal gate materials, and whether the process flow is “gate-first” or “gate-last.” The new transistors still maintain strain in the channel regions for maximum carrier mobility. Innovative design rules and advanced mask techniques will be used to extend the use of 193nm dry lithography, which we may assume includes orientation limitations in harmony with illumination sources. All these changes result in new process integration challenges and new yield-loss mechanisms, so we might expect it to take a while longer to ramp yield. Amazingly, Intel shows a 45nm yield-learning curve that tracks the last three nodes (see figure, above).

CEO Paul Otellini—dressed all in black like an international jewel thief, perhaps due to having spent excessive time around Steve Jobs—stated, “The plan is to have microprocessors in end-users hands by the end of 2007.”

Meanwhile, with timing that just could not be coincidence, on January 26th SEMATECH announced R&D; of a gate-first HK+dualMG process. “Be aware of the difference between a real manufacturing commitment, and research papers that continue to fall short of these results,” stated Intel's Bohr. The very next day IBM/AMD/Sony/Toshiba said that they will use HK+MG with their 45nm transistors sometime in 2008. We may assume that this announcement was rushed out in response to the Intel press release, since it erroneously refers to HK+MG as a single material—either the IBM alliance plans to use only one of the two, or IBM needs a technologist to review their press releases.

Technology development continues in the industry. Intel’s use of HK+MG materials in mainstream 45nm commercial manufacturing is certainly a significant milestone. Certainly other companies will follow, though in their own ways and in their own times. Due to the extreme complexities involved in any nanometer-era IC manufacturing, it’s getting more and more difficult to compare results from different companies. Fortunately, you can trust SST and WaferNEWS to sort the reality from the hype.


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Blogger Cyrus said...

I love the title of this thread, but it is clear that they are technology leaders. Nice web site.

Sun Feb 25, 11:13:00 PM PST  

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.