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070525: Intel-IBM fab hype-war and truths
Ed’s Threads 070525
Musings by Ed Korczynski on May 25, 2007

Intel-IBM fab hype-war and truths
It has been said that the first casualty of war is the truth…even more so in a hype-war. An interview appearing on a popular electronics industry Web site is the most recent battlefield in this ongoing hype-war between the world’s semiconductor manufacturing heavyweights. As tradeoffs in fab technology become more fundamental at 45nm nodes and beyond, different companies choose to deploy similar technologies in different ways. The truth is inherently complex and thus a bit complex to describe, and can die under the assault of hype.

Among fundamental choices today we find the following: double-patterned dry or single-patterned wet lithography for critical layer patterning, and use of porous or airgap low-k dielectric for on-chip multi-level interconnects. Intel has chosen double-patterned dry lithography and non-airgap low-k dielectrics. IBM has chosen single-patterned wet-lithography and airgap dielectrics.

As shown by Hoofman,, in the pages of SST last year, there are many different airgap process flows, which can produce many different airgap structures. Airgaps may be complete or partial between lines, and this is one of the more fundamental parameters to consider in integrating the structures into real chips. Thus, airgap1 is not airgap2 (General Semantics suggests the use of “indexing” to remind us of the essential distinctions between members of any conceptual set).

Using “complete airgap” flows and removing all dielectric between lines to achieve the absolute minimum capacitance does indeed create the two general problems articulated by Mark Bohr in the recorded interview: an expensive critical-lithography mask to ensure proper via landings, and copper electromigration sensitivity. However, the IBM flow uses airgaps only in the middle of line spaces while leaving dielectric material on the sidewalls of copper lines.

The IBM airgap process exposes parts of some metal sidewalls during the tricky three-stage gap etch, but the subsequent dielectric CVD process re-coats the exposed sidewall areas prior to “pinching off” the tops of gaps. With adequate sidewall dielectric in place, via landing and electromigration issues can be minimized if not avoided. Intel’s Bohr certainly understands airgap integration issues far better than I do, but because he’s not in a position to comment on how his competitor’s process might work, he accurately and properly expressed Intel’s results in the interview, and the generic disadvantages of approaches not currently taken by Intel.

However, a statement summarizing the interview reads thusly: “Mark Bohr, Intel senior fellow, says his company looked at air-gap technology like IBM recently introduced, and dismissed it as costly and inefficient.” That's a misinterpretation. The truth is that Intel never panned IBM’s airgap technology—Bohr answered a specific question about IBM’s technology with a generic answer about non-IBM technology. Of course, Bohr can very reasonably say that he has no knowledge if IBM’s technology beyond what is muddied in the official press release. Since IBM’s marketing spun the technology truth to the point of grandiose hype, it provides easy opportunity for Intel to comment on the hype instead of the truth. (Incidentally, further information on the general concept of self-assembled nanotechnology for lithographic masking applications can be found in the most recent issue of Microlithography World.)

The IBM hype was that no new lithography is needed. Intel counters that a generic process flow for airgaps requires critical-lithography steps. The truth is that the IBM flow does use an additional lithography step for each airgap level, but it’s non-critical and the mask generation has been automated as a button in the EDA deck. Critical-lithography steps for 45nm node processing can be 10X more expensive than non-critical patterning steps. If the IBM airgap process required critical lithography for each level then it might add 20%-25% to the cost of each chip, but with non-critical lithography it might add only 5%-8%.

For most people in the world who lack experience in fab processes, subtle complexities get lost in translation and details are distorted or lost. The truth about nanometer-era fab processes is that they are all tough to develop with inherent integration trade-offs. With Intel and IBM now going down divergent paths, it’s truly difficult to assess a fab technology “leader” in anything but hype.

— E.K.

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070525: Intel-IBM fab hype-war and truths

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Anonymous Dan Edelstein said...

We (IBM) have been wrongly portrayed as having chosen a different path, i.e. of airgaps instead of low-k or ultralow-k, and that we have “diverged.” (also wrong in implied added cost, mask/litho needs and criticality, and other pot-shots). In fact we were quite surprised at this misinterpretation - that concept was never stated by us nor meant to be implied. It's especially surprising given all the leading low-k and ultralow-k progress we have published and put into production. We are simply adding airgaps to our arsenal - as an option on top of a low-k baseline technology - not at the expense of the low-k insulator used in the baseline build to be gapped. Also please note there is no comparison between the wiring capacitances. Our airgap approach drops any given wiring capacitance by ~35%, regardless of how low the "k". Most chips would not require all levels to be gapped, if any. We think our high-end server CPU's will benefit the most.
For references on our leading low-k roadmap (which is lower-k than Intel's at each node), please refer to our 45-nm announcement at IEDM 2006, and prior papers on 90-nm and 65-nm at IITC 2004, IITC 2005, and AMC 2006. We are continuing our low-k reduction path, as our alliance partners, vendors, and customers know. We intend to keep pushing along the leading edge of low-k BEOL, and that in turn is underpinned by noteworthy experience developing those low-k materials, as well as understanding root causes for Cu reliability.
Airgaps are positioned on top of that baseline, reducing k by ~35% for just ~1% additional wafer cost per level gapped (and yes indeed, the added lithography is noncritical, and we didn't hold back in specifying that - it appeared in your first article, as well as Microprocessor Report May 21 and several others who published our process flow).
So to sum up, our airgap approach is a low-cost/high-performance option, selectable by chip and by wiring level, and fabricated on a competitive low-k BEOL baseline. The issue is not either/or, i.e. either gaps or low-k. It is simply whether one has this gapped option to offer, or not.

Tue Jun 12, 06:38:00 PM PDT  

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.