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070921: Flash and DRAM rule future of IC memory
Ed’s Threads 070921
Musings by Ed Korczynski on September 21, 2007

Flash and DRAM rule future of IC memory
A one-day technical symposium on “New Frontiers in Memory”, sponsored by the IEEE and Applied Materials, was held Sept. 20th at the Hotel Valencia in San Jose, CA. Amidst the ostentatious splendor of the flashy hotel, a standing-room-only crowd of technologists learned about the leading-edge of manufacturing the densest, fastest, cheapest IC memories. The takeaway theme: The two trains of DRAM and flash memory technologies have long “left the station” and unless and until they stop, other technologies such as phase-change RAM (PRAM) and magneto-resistance RAM (MRAM) will be relegated to niche applications.

Sung-Joo Hong, VP of R&D for Hynix, discussed the scaling limits of trench-DRAM technology determined by the control of subtle topography variations inside storage-node trenches. Retention time of the recess cell transistor will be challenged again with the introduction of 1.2V devices. With inherently smaller storage area and higher fields at junctions, extending current device architectures would result in excessively low retention time. The lowest equivalent oxide thickness (EOT) of 3Å in a 50:1 aspect ratio trench is not sufficient for 3Xnm node technology. Selective epitaxy and/or finFET (with p+ poly gates) are possible solutions, though DIBL is an inherent challenge for finFETs.

George Samachisa, VP of technology at SanDisk, showed that as flash capacity has improved while cost has dropped, it has come to overlap with hard disk drives (HDD) and DRAM/SRAM. With another 10x reduction in price, SanDisk projects that flash cost/bit could actually be less than DRAM. NAND flash costs ~$10/GB today, with ~$1.0/GB likely in 5-7 years time, and today's capacity of 16Gb/chip is expected to increase to 128-256Gb chips in 5-7 years. To continue scaling, the NAND and controller must work together for defect management, wear-out leveling, cell-cell interference mitigation, file/bad-block management, standard I/O, and DSP error-correction control to enable >2 bits/cell.

SanDisk has pushed five generations of technology in just as many years of production. In 2004 most production was 130nm, while by the end of this year the majority will be 70nm, and 2008 will be mostly 56nm with some 43nm in volume. Alternative NAND technologies (SONOS and TONOS) have so far not lived up to expectations, so SanDisk believes that floating gate is still the best candidate for scaling down to the 20nm technology node. Adding SONOS would allow NAND to be scaled one more node to 1Xnm, with 3D technology the likely successor.

Prof. H.S. Wong of Stanford U., formerly with IBM's T.J. Watson R&D center, discussed the bleeding-edge of “emerging memories” including change-storage, phase-change, nano-filament formation, ferroelectrics, magneto-resistance, stiction force, and mechanical deformation. Wong cautioned that any researcher observing hysteresis in physical phenomenon is tempted to claim a "new memory technology" -- but density, scalability, and manufacturing cost constraints tend to eliminate most from serious consideration.

Tom Andre, Freescale Semiconductor's head of toggle MRAM technology, explained that 0.18µm MRAM technology provides data retention of >20 years and unlimited endurance at 125°C for a 4Mb toggle MRAM running on 3.3V power supply and 26mm2 chip size (based on a 1.26µm2 cell size). The market space for fast and non-volatile memory allows for a price of US$4/Mb. Spin-torque MRAM, as opposed to the toggle variant, allows for more efficient writing based on current-density instead of energy transferred through a field. Distributions of write-currents can be a problem, particularly for the high-end where excessive currents can induce breakdowns.

PRAM seems promising, and the fact that ex-Intel-Flash-leader and CTO Stefan Lai has joined Ovonyx is encouraging, but this technology has been pushed for nearly 40 years by Energy Conversion Devices, Ovonyx's parent company. (This time for sure…) Samsung’s 512Mb PRAM in 90nm technology uses PN diodes, complex top contacts, and other unique processes on top of standard CMOS. Intel plans for PRAM production, too.

Metal-oxide memories have been shown with NiO, TiO, Nb2O5, Al2O5, Ta2O5, and Cr-doped perovskites. The exact mechanism is not clear, but some manner of conductive filament formation seems to be involved. Consequently, the on-current should be area-independent while the off-current should be area-dependent. Solid electrolytes such as Cu-WO3 and Cu-Cu2S could be used in the future, and theoretically scaled down to a single-atom between electrodes. HP’s crossbar nano-array architecture might fit into this categorization, too.

Any new memory technology must meet a market need, and must compete with DRAM and flash in terms of cost and functionality. “There’s a lot of room to scale DRAM before we need new memory technology,” said Applied Materials Fellow Reza Arghavani, in an exclusive interview with WaferNEWS. Arghavani points out that equipment companies can bring to memory manufacturing innovations that have been in use in logic fabs for generations, such as copper interconnects, epi-layers, HK+MG, and low-k dielectrics. “They have to be re-optimized and re-integrated, but fundamentally they are the same technologies,” he said. Charge-trap memories are just like HK+MG stacks, in the need for work-function engineering of the materials interfaces, he pointed out. “The physics of it is identical.”

For at least the last few nodes, logic has driven thin-films and new materials development, while memory has driven lithography development. “Flash is driving litho resolution, while overlay is currently being driven by DRAM,” clarified Rudi Hendel, Applied Materials' managing director, technology programs, in an exclusive interview with WaferNEWS.

Humans like to sort and store information, and the ever-greater ability to store data in digital form continues to spur demand for IC memory. SanDisk presented recent data (May 2007) from Gartner Dataquest that forecasted NAND bit demand will increase 40x from 2006 to 2011, with major demand for PC, mobile phones, USB, and media players. In the last ten years, flash has already replaced a host of older storage mediums (35mm film, floppy/Zip/Clik/tape drives) and is well on the way to replacing CDs and ultra-small HDD (<1.3”). The message is clear -- other promising memory technologies have a tough train to catch.


A comment (below) that this blog entry does not distinguish between stand-alone and embedded applications is certainly correct; stand-alone memory IC technology can be more easily compared in terms of cost/density/performance, while embedded applications must consider additional cost and performance increases. Such analysis is a bit beyond the scope of what can be covered in a relatively short blog entry.

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070921: Flash and DRAM rule future of IC memory

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Anonymous Anonymous said...

A distinction has not been made between stand-alone and embedded memory.

Wed Sep 26, 12:25:00 AM PDT  

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.